Using Dual-Supply, Dual-Threshold and Tansisto Sizing to Reduce Power in Digital Integrated Circuits

S. A. Augsburger

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M02/6

2002

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http://www2.eecs.berkeley.edu/Pubs/TechRpts/2002/Archive/ERL-02-6.pdf

BibTeX citation:

@techreport{Augsburger:M02/6,
    Author= {Augsburger, S. A.},
    Title= {Using Dual-Supply, Dual-Threshold and Tansisto Sizing to Reduce Power in Digital Integrated Circuits},
    Year= {2002},
    Month= {Apr},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2002/3966.html},
    Number= {UCB/ERL M02/6},
}

EndNote citation:

%0 Report
%A Augsburger, S. A. 
%T Using Dual-Supply, Dual-Threshold and Tansisto Sizing to Reduce Power in Digital Integrated Circuits
%I EECS Department, University of California, Berkeley
%D 2002
%@ UCB/ERL M02/6
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2002/3966.html
%F Augsburger:M02/6