Qi Zhu and Farhana Sheikh and Philip Chong

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-133

October 19, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-133.pdf

A voltage-island architecture for systems-on-chip is an effective way to reduce active and static power. For such multiple supply designs, various layout architectures exist; however, placement algorithms that take advantage of a circuit rows style of implementation are not available to designers today. This paper presents two algorithms to place standard cells in a circuit rows style of implementation for dual-supply digital designs using double-height level converting flip-flops. Our results show significant improvement in terms of wirelength over a simple bi-partitioning scheme that is currently employed in manufactured designs. On average, we show a 21% wiring overhead for multiple-supply design using our new techniques compared to an 81% overhead under the bi-partitioning scheme. This paper represents a first work quantifying the physical design overhead of a dual-supply system in the context of multiple-supply aware placement algorithms.

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BibTeX citation:

@techreport{Zhu:EECS-2006-133,
    Author= {Zhu, Qi and Sheikh, Farhana and Chong, Philip},
    Title= {A Placement Technique for Multiple-Voltage Design},
    Year= {2006},
    Month= {Oct},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-133.html},
    Number= {UCB/EECS-2006-133},
    Abstract= {A voltage-island architecture for systems-on-chip is an effective way to reduce active and static power. For such multiple supply designs, various layout architectures exist; however, placement algorithms that take advantage of a circuit rows style of implementation are not available to designers today.  This paper presents two algorithms to place standard cells in a circuit rows style of implementation for dual-supply digital designs using double-height level converting flip-flops. Our results show significant improvement in terms of wirelength over a simple bi-partitioning scheme that is currently employed in manufactured designs.  On average, we show a 21% wiring overhead for multiple-supply design using our new techniques compared to an 81% overhead under the bi-partitioning scheme. This paper represents a first work quantifying the physical design overhead of a dual-supply system in the context of multiple-supply aware placement algorithms.},
}

EndNote citation:

%0 Report
%A Zhu, Qi 
%A Sheikh, Farhana 
%A Chong, Philip 
%T A Placement Technique for Multiple-Voltage Design
%I EECS Department, University of California, Berkeley
%D 2006
%8 October 19
%@ UCB/EECS-2006-133
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-133.html
%F Zhu:EECS-2006-133