Alessandro Pinto and Luca Carloni and Alberto L. Sangiovanni-Vincentelli

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-137

October 24, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-137.pdf

We propose an efficient design flow for the automatic synthesis of Network-on-Chip (NOC) topologies. The specification of the problem is given as a netlist of IP cores and their communication requirements. Each IP is characterized by its area. A communication constraint is denoted by its source and destination IP and a minimum bandwidth requirement. Together with the specification, the users provides a percentage of the chip area that they want to allocate for the communication network.

Then, given the clock period of the network (that we assume to be synchronous), and a target technology, the proposed design flow explores the entire topology space and returns an optimal NOC where each router has a position and a routing table assigned. We consider two optimality criteria: power consumption and power delay product. Our design flow, which is based on an approximation algorithm, is efficient and highlights the delicate trade-off balance between cost of communication and cost of switching.

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BibTeX citation:

@techreport{Pinto:EECS-2006-137,
    Author= {Pinto, Alessandro and Carloni, Luca and Sangiovanni-Vincentelli, Alberto L.},
    Title= {Synthesis of Low Power NOC Topologies under Bandwidth Constraints},
    Year= {2006},
    Month= {Oct},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-137.html},
    Number= {UCB/EECS-2006-137},
    Abstract= {We propose an efficient design flow for the automatic synthesis of 
Network-on-Chip (NOC)  
topologies. 
The specification of the problem is given as a netlist of IP cores and their
communication requirements. Each IP is characterized by its area. 
A communication constraint is denoted by its source and destination IP and
a minimum bandwidth requirement.  Together with the specification, the users
provides a percentage of the chip area that they want to allocate for the
communication network.   

Then, given the clock period of the network (that we assume to be synchronous),
and a target technology, the proposed design flow explores the entire topology
space and returns an optimal NOC where each router has a position and a routing
table assigned. 
We consider two optimality criteria:
power consumption and power delay product. 
Our design flow, which is based on an approximation algorithm, 
is efficient and highlights the delicate trade-off balance between cost of
communication and cost of switching.},
}

EndNote citation:

%0 Report
%A Pinto, Alessandro 
%A Carloni, Luca 
%A Sangiovanni-Vincentelli, Alberto L. 
%T Synthesis of Low Power NOC Topologies under Bandwidth Constraints
%I EECS Department, University of California, Berkeley
%D 2006
%8 October 24
%@ UCB/EECS-2006-137
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-137.html
%F Pinto:EECS-2006-137