Radu Zlatanovici

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-164

December 10, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-164.pdf

In recent years, power has become the most important limiting factor for electronic circuits. This has prompted a shift in the design paradigm for digital circuits: the traditional approach of achieving the highest performance by increasing the clock frequency has been replaced by a joint optimization for both power and performance. This thesis puts into practice the new design paradigm for the power - constrained era: design as a power - performance optimization problem. The new circuit optimization framework provides a systematic methodology for the power - performance optimization of custom digital circuits at circuit and microarchitecture levels and is demonstrated on several examples. The circuit optimization framework formulates the design as a mathematical optimization problem that is solved numerically. The user can select a wide array of models for the underlying technology, optimization variables, design goals and design constraints, with varying impacts on the convergence speed and the accuracy of the solutions. The formulation exploits the mathematical properties of the resulting optimization problems and in some cases can guarantee the global optimality of the solutions or verify their quality against a near-optimality boundary. Four examples are used throughout the thesis to demonstrate the circuit optimization framework: - a 64-bit Kogge-Stone static CMOS carry tree, to demonstrate the impact of adjusting different sets of design variables (like gate sizes, supply voltage and threshold voltage) in the power - performance optimization problem; - a detailed study of 64-bit carry lookahead adders in 90nm CMOS, to illustrate how the circuit optimization framework can be used to build intuition into the subtle tradeoffs of a particular family of circuits; - an IEEE-compliant single-precision fused multiply-add Floating Point Unit (FPU) in 90nm CMOS, to compare the circuit optimization framework with a commercial logic synthesis tool; - a 64-bit Kogge-Stone static CMOS carry tree, to demonstrate how process variations can be included in a yield-constrained power - performance optimization. One circuit from the 64-bit adder family in the second example has been built in silicon in order to confirm the correct operation of the framework through measurement. The 90nm chip performs single-cycle 64-bit additions in 240ps and consumes 260mW at the nominal supply voltage of 1V.

Advisors: Borivoje Nikolic

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BibTeX citation:

@phdthesis{Zlatanovici:EECS-2006-164,
    Author= {Zlatanovici, Radu},
    Title= {Power - Performance Optimization for Digital Circuits},
    School= {EECS Department, University of California, Berkeley},
    Year= {2006},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-164.html},
    Number= {UCB/EECS-2006-164},
    Abstract= {In recent years, power has become the most important limiting factor for electronic circuits. This has prompted a shift in the design paradigm for digital circuits: the traditional approach of achieving the highest performance by increasing the clock frequency has been replaced by a joint optimization for both power and performance.
This thesis puts into practice the new design paradigm for the power - constrained era: design as a power - performance optimization problem. The new circuit optimization framework provides a systematic methodology for the power - performance optimization of custom digital circuits at circuit and microarchitecture levels and is demonstrated on several examples. 
The circuit optimization framework formulates the design as a mathematical optimization problem that is solved numerically. The user can select a wide array of models for the underlying technology, optimization variables, design goals and design constraints, with varying impacts on the convergence speed and the accuracy of the solutions. The formulation exploits the mathematical properties of the resulting optimization problems and in some cases can guarantee the global optimality of the solutions or verify their quality against a near-optimality boundary.
Four examples are used throughout the thesis to demonstrate the circuit optimization framework:
- a 64-bit Kogge-Stone static CMOS carry tree, to demonstrate the impact of adjusting different sets of design variables (like gate sizes, supply voltage and threshold voltage) in the power - performance optimization problem;
- a detailed study of 64-bit carry lookahead adders in 90nm CMOS, to illustrate how the circuit optimization framework can be used to build intuition into the subtle tradeoffs of a particular family of circuits;
- an IEEE-compliant single-precision fused multiply-add Floating Point Unit (FPU) in 90nm CMOS, to compare the circuit optimization framework with a commercial logic synthesis tool;
- a 64-bit Kogge-Stone static CMOS carry tree, to demonstrate how process variations can be included in a yield-constrained power - performance optimization.
One circuit from the 64-bit adder family in the second example has been built in silicon in order to confirm the correct operation of the framework through measurement. The 90nm chip performs single-cycle 64-bit additions in 240ps and consumes 260mW at the nominal supply voltage of 1V.},
}

EndNote citation:

%0 Thesis
%A Zlatanovici, Radu 
%T Power - Performance Optimization for Digital Circuits
%I EECS Department, University of California, Berkeley
%D 2006
%8 December 10
%@ UCB/EECS-2006-164
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-164.html
%F Zlatanovici:EECS-2006-164