Design Methodology for Run-time Management of Reconfigurable Digital Signal Processor Systems
Roy Allen Sutton
EECS Department, University of California, Berkeley
Technical Report No. UCB/EECS-2006-63
May 17, 2006
http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-63.pdf
In recent years, significant attention has been given to emerging reconfigurable digital signal processing (DSP) systems. They can undergo in-system hardware changes in order to adapt to post-design external variations in system constraints, stimulus, algorithms, and optimization objectives. This adds degrees of freedom and levels of complexity to the design process that are not well considered by contemporary computer aided design (CAD) methods. This research presents a methodology and CAD design environment, based in a quantitative approach, that support the implementation of domain-specific DSP systems which cope with post-design changes by leveraging reconfigurable hardware architectures.
Run-time methods and dynamic reconfiguration comes at the costs of overheads. The proposed methodology limits these overheads by imposing a framework that creates multiple pre-characterized templated-mapping design implementations that are organized as candidates under the discrimination of one or more system schedulers. At run-time, the managing scheduler selects implementations according to its assigned optimization objective given the resource availability. To deal with the tight constraints on cost-performance inherent within DSP systems, the framework introduces mapping modes that further guide and/or limit run-time scheduler choice in template selection (dynamic resource "type" allocation), resource binding, and configuration. These modes allow for design-time trade-offs between predictability and flexibility. A formal model that defines the components and their interactions is presented to provide some rigor in the methodology application.
A design environment and tools development framework is presented that adheres to the methodology and formal model. It includes a simulator for use in quantitative design exploration. The framework accounts for use-costs in computation, communication, and reconfiguration in terms of area, energy, as well as time. Others metrics of interest (such as position, etc.) can be easily incorporated. Detailed quantitative statistics for system behavior are accounted for and visually presented. This aids the designer during iterative design refinement. Moreover, performance metrics can be analyzed at run-time by system schedulers as a guide for statistical-based adaptation.
The effectiveness of the proposed methodology is demonstrated across a database of generated designs and for an actual multi-user DSP system design. The results for each are presented in separate chapters. The appendix includes a tutorial that discusses the environment, framework, an existing CAD tools.
Advisors: Jan M. Rabaey
BibTeX citation:
@phdthesis{Sutton:EECS-2006-63,
Author= {Sutton, Roy Allen},
Title= {Design Methodology for Run-time Management of Reconfigurable Digital Signal Processor Systems},
School= {EECS Department, University of California, Berkeley},
Year= {2006},
Month= {May},
Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-63.html},
Number= {UCB/EECS-2006-63},
Abstract= {In recent years, significant attention has been given to emerging reconfigurable digital signal processing (DSP) systems. They can undergo in-system hardware changes in order to adapt to post-design external variations in system constraints, stimulus, algorithms, and optimization objectives. This adds degrees of freedom and levels of complexity to the design process that are not well considered by contemporary computer aided design (CAD) methods. This research presents a methodology and CAD design environment, based in a quantitative approach, that support the implementation of domain-specific DSP systems which cope with post-design changes by leveraging reconfigurable hardware architectures.
Run-time methods and dynamic reconfiguration comes at the costs of overheads. The proposed methodology limits these overheads by imposing a framework that creates multiple pre-characterized templated-mapping design implementations that are organized as candidates under the discrimination of one or more system schedulers. At run-time, the managing scheduler selects implementations according to its assigned optimization objective given the resource availability. To deal with the tight constraints on cost-performance inherent within DSP systems, the framework introduces mapping modes that further guide and/or limit run-time scheduler choice in template selection (dynamic resource "type" allocation), resource binding, and configuration. These modes allow for design-time trade-offs between predictability and flexibility. A formal model that defines the components and their interactions is presented to provide some rigor in the methodology application.
A design environment and tools development framework is presented that adheres to the methodology and formal model. It includes a simulator for use in quantitative design exploration. The framework accounts for use-costs in computation, communication, and reconfiguration in terms of area, energy, as well as time. Others metrics of interest (such as position, etc.) can be easily incorporated. Detailed quantitative statistics for system behavior are accounted for and visually presented. This aids the designer during iterative design refinement. Moreover, performance metrics can be analyzed at run-time by system schedulers as a guide for statistical-based adaptation.
The effectiveness of the proposed methodology is demonstrated across a database of generated designs and for an actual multi-user DSP system design. The results for each are presented in separate chapters. The appendix includes a tutorial that discusses the environment, framework, an existing CAD tools.},
}
EndNote citation:
%0 Thesis %A Sutton, Roy Allen %T Design Methodology for Run-time Management of Reconfigurable Digital Signal Processor Systems %I EECS Department, University of California, Berkeley %D 2006 %8 May 17 %@ UCB/EECS-2006-63 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-63.html %F Sutton:EECS-2006-63