Standby Power Management Architecture for Deep-Submicron Systems

Michael Alan Sheets

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-70

May 19, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-70.pdf

In deep-submicron processes a significant portion of the power budget is lost in standby power due to increasing leakage effects. For systems that have long idle times punctuated by bursts of activity, such as PDAs, cell-phones, and wireless sensor networks nodes, this standby power consumption reduces the effectiveness of duty-cycling. This work surveys a number of subthreshold leakage reduction techniques and identifies supply rail gating (MTCMOS) as the most promising. MTCMOS is a dynamic technique that has two distinct modes: an active processing mode and a lower power sleep mode.

The smallest area implementations of MTCMOS have the side-effect of losing the state of the system when in sleep mode. This complicates the resumption of the active mode, because traditional designs are intolerent to the loss of state. This work presents a general framework to reduce the state maintainence requirements during sleep mode, without losing information required to resume the active mode. The framework is applied to finite state machines and microprocessors, since these are commonly used in system design.

Partitioning the system into subsystems with individually controlled supply rails (termed power domains) allows fine-grain control of the power mode for portions of the chip. Each power domain must be dynamically put in the appropriate power mode to ensure correct system operation while minimizing power consumption. This control logic collectively forms the core of a power manager. Most power manager implementation approaches are largely ad-hoc and custom designed for each application.

This work presents a structured methodology and architecture for the implementation and control of power domains to form a power managed system. Approaches to the partitioning and implementation of individual power domains are explored. The functional requirements for the power manager are examined, including the physical and temporal composition of the power domains.

This methodology and architecture are demonstrated on the protocol processor for the PicoRadio wireless sensor network node. The Charm test chip, implemented in 130nm CMOS, uses supply rail gating for eight power domains to reduce standby power 92%.

Advisors: Jan M. Rabaey

BibTeX citation:

@phdthesis{Sheets:EECS-2006-70,
    Author= {Sheets, Michael Alan},
    Title= {Standby Power Management Architecture for Deep-Submicron Systems},
    School= {EECS Department, University of California, Berkeley},
    Year= {2006},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-70.html},
    Number= {UCB/EECS-2006-70},
    Abstract= {In deep-submicron processes a significant portion of the power budget is lost in standby power due to increasing leakage effects.  For systems that have long idle times punctuated by bursts of activity, such as PDAs, cell-phones, and wireless sensor networks nodes, this standby power consumption reduces the effectiveness of duty-cycling.  This work surveys a number of subthreshold leakage reduction techniques and identifies supply rail gating (MTCMOS) as the most promising.  MTCMOS is a dynamic technique that has two distinct modes: an active processing mode and a lower power sleep mode.

The smallest area implementations of MTCMOS have the side-effect of losing the state of the system when in sleep mode.  This complicates the resumption of the active mode, because traditional designs are intolerent to the loss of state.  This work presents a general framework to reduce the state maintainence requirements during sleep mode, without losing information required to resume the active mode.  The framework is applied to finite state machines and microprocessors, since these are commonly used in system design.  

Partitioning the system into subsystems with individually controlled supply rails (termed power domains) allows fine-grain control of the power mode for portions of the chip.  Each power domain must be dynamically put in the appropriate power mode to ensure correct system operation while minimizing power consumption.  This control logic collectively forms the core of a power manager.  Most power manager implementation approaches are largely ad-hoc and custom designed for each application.

This work presents a structured methodology and architecture for the implementation and control of power domains to form a power managed system.  Approaches to the partitioning and implementation of individual power domains are explored.  The functional requirements for the power manager are examined, including the physical and temporal composition of the power domains.

This methodology and architecture are demonstrated on the protocol processor for the PicoRadio wireless sensor network node.  The Charm test chip, implemented in 130nm CMOS, uses supply rail gating for eight power domains to reduce standby power 92%.},
}

EndNote citation:

%0 Thesis
%A Sheets, Michael Alan 
%T Standby Power Management Architecture for Deep-Submicron Systems
%I EECS Department, University of California, Berkeley
%D 2006
%8 May 19
%@ UCB/EECS-2006-70
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-70.html
%F Sheets:EECS-2006-70