Tina Harriet Smilkstein

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2007-96

August 6, 2007

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-96.pdf

As clocking speeds increase, it becomes more and more important to be able to generate ¿clean¿, low-jitter clock signals. Traditionally, PLLs have been one of the most commonly used signal cleaning methods, but as higher frequencies are being used, the limits imposed by both the design complexity and performance of PLLs is being felt. This work shows that a purely feedforward jitter removal circuit is possible for frequencies in the 800MHz to 5GHz range. The design is relatively simple and modular, which allows a designer to customize to the type of system where the circuit will be used. MOSFET devices were used and no special processing is required. In some cases it is recommended that certain analog blocks are placed near each other to minimize process variation effects but, other than that, no special layout considerations are required or recommended. The transistors used in the switching NMOS in the integrator have a channel length of 110nm. All other devices in the design are sized above 130nm. No effort was made to minimize the number of transistors used. The final number of transistors used was 403 from the input single-to-differential converter through the output level detector. Exactly 300 of these were used in the input monostable block. Simulations were done using ST Microelectronic 90nm technology. Simulations looked at the performance of the circuit in the presence of supply noise, GND noise, intrinsic noise,and input jitter. All simulations were done at typical, fast, and slow corners. Attenuation of jitter was tested with input jitter from 0pspk −pk to the limit the system could process. For a system running at 1GHz and driven with a pulse of width 650ps, the maximum jitter that can be processed is slightly less than 350pspk −pk. The results varied from −13.81dB (a 4.9x reduction in rms jitter) for 200mV of random noise on the supply, intrinsic noise, and worst case evaluations for 10% process variation, to −14.68dB (a 5.4x reduction in rms jitter) for no supply or GND noise. Using an ideal source instead of the pre-processing input monostable block used in these results, gives a maximum jitter reduction of −35.5dB. The loss in performance can be attributed to the large amount of circuitry in the input block. These results show that this purely feedforward system is, in fact, effective in reducing jitter. In implementing this system, a number of new blocks were developed including a differential Schmitt trigger, feedforward correction block to align signals, high-speed pulse-mode flip-flop, and a monostable that can produce a duty cycle close to 100%. The feedforward biasing circuitry was also unique as was the effort to create a completely feedforward design.

Advisors: Robert W. Brodersen

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BibTeX citation:

@phdthesis{Smilkstein:EECS-2007-96,
    Author= {Smilkstein, Tina Harriet},
    Title= {Jitter Reduction on High-Speed Clock Signals},
    School= {EECS Department, University of California, Berkeley},
    Year= {2007},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-96.html},
    Number= {UCB/EECS-2007-96},
    Abstract= {As clocking speeds increase, it becomes more and more important to be able to generate ¿clean¿, low-jitter clock signals. Traditionally, PLLs have been one of the most commonly used signal cleaning methods, but as higher frequencies are being used, the limits imposed by both the design complexity and performance of PLLs is being felt. This work shows that a purely feedforward jitter removal circuit is possible for frequencies in the 800MHz to 5GHz range. The design is relatively simple and modular, which allows a designer to customize to the type of system where the circuit will be used. MOSFET devices were used and no special processing is required. In some cases it is recommended that certain analog blocks are placed near each other to minimize process variation effects but, other than that, no special layout considerations are required or recommended. The transistors used in the switching NMOS in the integrator have a channel length of 110nm. All other devices in the design are sized above 130nm. No effort was made to minimize the number of transistors used. The final number of transistors used was 403 from the input single-to-differential converter through the output level detector. Exactly 300 of these were used in the input monostable block.
Simulations were done using ST Microelectronic 90nm technology. Simulations looked at the performance of the circuit in the presence of supply noise, GND noise, intrinsic noise,and input jitter. All simulations were done at typical, fast, and slow corners. Attenuation of jitter was tested with input jitter from 0pspk −pk to the limit the system could process. For a system running at 1GHz  and driven with a pulse of width 650ps, the maximum jitter that can be processed is slightly less than 350pspk −pk. The results varied from −13.81dB (a 4.9x reduction in rms jitter) for 200mV of random noise on the supply, intrinsic noise, and worst case evaluations for 10% process variation, to −14.68dB (a 5.4x reduction in rms jitter) for no supply or GND noise. Using an ideal source instead of the pre-processing input monostable block used in these results, gives a maximum jitter reduction of −35.5dB. The loss in performance can be attributed to the large amount of circuitry in the input block. These results show that this purely feedforward system is, in fact, effective in reducing jitter.
In implementing this system, a number of new blocks were developed including a differential Schmitt trigger, feedforward correction block to align signals, high-speed pulse-mode flip-flop, and a monostable that can produce a duty cycle close to 100%. The feedforward biasing circuitry was also unique as was the effort to create a completely feedforward design.},
}

EndNote citation:

%0 Thesis
%A Smilkstein, Tina Harriet 
%T Jitter Reduction on High-Speed Clock Signals
%I EECS Department, University of California, Berkeley
%D 2007
%8 August 6
%@ UCB/EECS-2007-96
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-96.html
%F Smilkstein:EECS-2007-96