Liang Teck Pang

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2008-108

August 29, 2008

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-108.pdf

The scaling of CMOS technology into the deep sub-micron regime has resulted in increased impact of process variability on circuits, to the point where it is considered a major bottleneck to further scaling. In order to continue scaling, there is a need to reduce margins in the design by classifying process variations as systematic or random. In this work, a methodology to characterize variability through measurement and analysis has been developed. Systematic and random, die-to-die (D2D) and within-die (WID) components of variability are quantified and corresponding sources of variability are identified. This methodology was developed for an early 90nm CMOS process and further refined for an early 45nm CMOS process. Test-chips have been designed to study the effects of layout, and characterize variability of delay and leakage current using an array of test-structures. Delay is obtained through the measurement of ring oscillator frequencies, and transistor leakage current is measured by an on-chip analog-to-digital converter (ADC). Measurement and analysis results for the 90nm and 45nm processes will be shown to demonstrate the effectiveness of this methodology in characterizing process variability.

Advisors: Borivoje Nikolic

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BibTeX citation:

@phdthesis{Pang:EECS-2008-108,
    Author= {Pang, Liang Teck},
    Title= {Measurement and Analysis of Variability in CMOS circuits},
    School= {EECS Department, University of California, Berkeley},
    Year= {2008},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-108.html},
    Number= {UCB/EECS-2008-108},
    Abstract= {The scaling of CMOS technology into the deep sub-micron regime has resulted in increased impact of process variability on circuits, to the point where it is considered a major bottleneck to further scaling. In order to continue scaling, there is a need to reduce margins in the design by classifying process variations as systematic or random. In this work, a methodology to characterize variability through measurement and analysis has been
developed. Systematic and random, die-to-die (D2D) and within-die (WID) components of variability are quantified and corresponding sources of variability are identified.
This methodology was developed for an early 90nm CMOS process and further refined for an early 45nm CMOS process. Test-chips have been designed to study the effects of layout, and characterize variability of delay and leakage current using an array of test-structures. Delay is obtained through the measurement of ring oscillator frequencies, and transistor leakage current is measured by an on-chip analog-to-digital converter (ADC). 
Measurement and analysis results for the 90nm and 45nm processes will be shown to demonstrate the effectiveness of this methodology in characterizing process variability.},
}

EndNote citation:

%0 Thesis
%A Pang, Liang Teck 
%T Measurement and Analysis of Variability in CMOS circuits
%I EECS Department, University of California, Berkeley
%D 2008
%8 August 29
%@ UCB/EECS-2008-108
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-108.html
%F Pang:EECS-2008-108