Hiren D. Patel and Ben Lickly and Bas Burgers and Edward A. Lee

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2008-115

September 12, 2008

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-115.pdf

The precision timed architecture presents a real-time embedded processor with instruction-set extensions that provide precise timing control via timing instructions to the programmer. Programmers not only describe their functionality using C, but they can also prescribe timing requirements in the program. We target this architecture and present a static scratchpad memory allocation scheme that greedily attempts to meet these timing requirements. Our objective is to schedule minimum number of instructions and minimize data allocation to the scratchpads such that timing requirements in the program are met. Once the timing requirements are satisfied, the remainder of the scratchpad memory can be used to optimize some other metric desired by the programmer. As an example, we minimize the frequency of main memory accesses in the program. This work presents the following: 1) high-level timing constructs for C that synthesize to timing instructions and 2) a greedy iterative instruction and data scratchpad memory allocation scheme that attempts to first meet the specified timing requirements.

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BibTeX citation:

@techreport{Patel:EECS-2008-115,
    Author= {Patel, Hiren D. and Lickly, Ben and Burgers, Bas and Lee, Edward A.},
    Title= {A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture},
    Year= {2008},
    Month= {Sep},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-115.html},
    Number= {UCB/EECS-2008-115},
    Abstract= {The precision timed architecture presents a real-time embedded processor with instruction-set extensions that provide precise timing control via timing instructions to the programmer. Programmers not only describe their functionality using C, but they can also prescribe timing requirements in the program. We target this architecture and present a static scratchpad memory allocation scheme that greedily attempts to meet these timing requirements.
Our objective is to schedule minimum number of instructions and minimize data allocation to the scratchpads such that timing requirements in the program are met. Once the timing requirements are satisfied, the remainder of the scratchpad memory can be used to optimize  some other metric desired by the programmer. As an example, we minimize the frequency of main memory accesses in the program. This work presents the following: 1) high-level timing constructs for C that synthesize to timing instructions and 2) a greedy iterative instruction and data scratchpad memory allocation scheme that attempts to first meet the specified timing requirements.},
}

EndNote citation:

%0 Report
%A Patel, Hiren D. 
%A Lickly, Ben 
%A Burgers, Bas 
%A Lee, Edward A. 
%T A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture
%I EECS Department, University of California, Berkeley
%D 2008
%8 September 12
%@ UCB/EECS-2008-115
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-115.html
%F Patel:EECS-2008-115