Dominic Aldo Antonelli and Alan J. Smith and Jan-Willem van de Waerdt

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2008-24

March 21, 2008

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-24.pdf

Peak power and total energy consumption are key factors in the design of embedded microprocessors. Many techniques have been shown to provide great reductions in peak power and/or energy consumption. Unfortunately, several unrealistic assumptions are often made in research studies, especially in regards to multimedia processors. This paper focusses on power reduction is real commercial processors, and how that differs from more abstract research studies.

First, such processors often already utilize several power reduction techniques, and these existing optimizations can have a huge impact on the effectiveness of further optimizations. Second, highly optimized production code tends to have significantly less schedule slack and significantly higher density of memory accesses than unoptimized code. Finally, many such studies are done using high-level simulators, which may not accurately model the power consumption of real microprocessors. In addition, in this study we focus on an embedded, synthesized processor, rather than a high performance custom and hand designed stand-alone microprocessor; a 400MHz synthesized core (the TriMedia TM3270) has significantly different characteristics than a 3GHz Pentium.

We carefully analyze the power consumption of the TriMedia TM3270, a commercial product, on both reference benchmark code and optimized code. We use commercial synthesis and simulation tools to obtain a detailed breakdown of where power is consumed. We find that increased functional unit utilization causes significant differences in power consumption between unoptimized and carefully hand-optimized code. We also apply some simple techniques for power savings with no performance degradation, and find that such techniques can greatly change the power profile of a microprocessor. We find that clock gating of individual functional units is vital to keeping the dynamic power low. Finally, we find that synthesizing for the fastest target frequency possible at a given voltage yields the most energy-efficient design.

Advisors: Alan J. Smith

---

BibTeX citation:

@mastersthesis{Antonelli:EECS-2008-24,
    Author= {Antonelli, Dominic Aldo and Smith, Alan J. and van de Waerdt, Jan-Willem},
    Title= {Power Consumption in a Real, Commercial Multimedia Core},
    School= {EECS Department, University of California, Berkeley},
    Year= {2008},
    Month= {Mar},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-24.html},
    Number= {UCB/EECS-2008-24},
    Abstract= {Peak power and total energy consumption are key factors in the design
of embedded microprocessors.  Many techniques have been shown to
provide great reductions in peak power and/or energy consumption.
Unfortunately, several unrealistic assumptions are often made in
research studies, especially in regards to multimedia processors.
This paper focusses on power reduction is real commercial processors,
and how that differs from more abstract research studies.

First, such processors often already utilize several power reduction
techniques, and these existing optimizations can have a huge impact
on the effectiveness of further optimizations.  Second, highly
optimized production code tends to have significantly less schedule
slack and significantly higher density of memory accesses than
unoptimized code. Finally, many such studies are done using
high-level simulators, which may not accurately model the power
consumption of real microprocessors.  In addition, in this study we
focus on an embedded, synthesized processor, rather than a high
performance custom and hand designed stand-alone microprocessor; a
400MHz synthesized core (the TriMedia TM3270) has significantly
different characteristics than a 3GHz Pentium.

We carefully analyze the power consumption of the TriMedia TM3270, a
commercial product, on both reference benchmark code and optimized
code.  We use commercial synthesis and simulation tools to obtain a
detailed breakdown of where power is consumed.  We find that
increased functional unit utilization causes significant differences
in power consumption between unoptimized and carefully hand-optimized
code.  We also apply some simple techniques for power savings with no
performance degradation, and find that such techniques can greatly
change the power profile of a microprocessor. We find that clock
gating of individual functional units is vital to keeping the dynamic
power low. Finally, we find that synthesizing for the fastest target
frequency possible at a given voltage yields the most
energy-efficient design.},
}

EndNote citation:

%0 Thesis
%A Antonelli, Dominic Aldo 
%A Smith, Alan J. 
%A van de Waerdt, Jan-Willem 
%T Power Consumption in a Real, Commercial Multimedia Core
%I EECS Department, University of California, Berkeley
%D 2008
%8 March 21
%@ UCB/EECS-2008-24
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-24.html
%F Antonelli:EECS-2008-24