Ben Lickly and Isaac Liu and Sungjun Kim and Hiren D. Patel and Stephen A. Edwards and Edward A. Lee

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2008-40

April 18, 2008

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-40.pdf

In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees.

We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.

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BibTeX citation:

@techreport{Lickly:EECS-2008-40,
    Author= {Lickly, Ben and Liu, Isaac and Kim, Sungjun and Patel, Hiren D. and Edwards, Stephen A. and Lee, Edward A.},
    Title= {Predictable Programming on a Precision Timed Architecture},
    Year= {2008},
    Month= {Apr},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-40.html},
    Number= {UCB/EECS-2008-40},
    Note= {This paper has been accepted for publication at CASES 2008.},
    Abstract= {In a hard real-time embedded system, the time at which a result is computed is as important as the result itself.  Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies,
but without precise worst-case execution time bounds they cannot provide guarantees.

We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control.  Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed
memory hierarchy provides predictable latency.  We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.},
}

EndNote citation:

%0 Report
%A Lickly, Ben 
%A Liu, Isaac 
%A Kim, Sungjun 
%A Patel, Hiren D. 
%A Edwards, Stephen A. 
%A Lee, Edward A. 
%T Predictable Programming on a Precision Timed Architecture
%I EECS Department, University of California, Berkeley
%D 2008
%8 April 18
%@ UCB/EECS-2008-40
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-40.html
%F Lickly:EECS-2008-40