Kevin Brandon Camera

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2008-80

June 9, 2008

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-80.pdf

Reconfigurable hardware devices, such as field-programmable gate arrays (FPGAs), have been shown to achieve greater net throughput and power, energy, and cost efficiency compared to traditional microprocessors in high-performance computing and signal processing applications. The primary drawback to the use of such devices, however, is the perceived difficulty of the overall programming process, which includes the complete design and verification of the system.

In an attempt alleviate this net system design problem, the approach of <i>direct verification</i> was conceived and implemented on the BEE2 hardware platform. Direct verification utilizes the resources of the platform to provide variables in the hardware domain, which feature read/write access to data, runtime streaming of data to off-chip storage, and fully automated dynamic assertion checking. By regulating the design clock, the verification infrastructure can also control the execution of the design under test, both via manual interaction and same-cycle breakpoints triggered by variable assertion failures. In addition, all this functionality is accessible in the original design environment via a remote network service provided by the software layer of the verification infrastructure, which allows data to be generated and analyzed at the same level of abstraction previously only present during simulation.

The resource requirements to enable direct verification on the BEE2 platform were measured both independently and as part of two real-world design examples. The base infrastructure was found to occupy about 12% of an XCV2P70 FPGA (8% of which was purely due to the DDR2 memory controller), and the addition of a typical 16-bit variable required 75 logic slices (0.23% of the device) on average. The operating frequency of the design under test is not severely impacted unless the device utilization approaches 100%, and runtime system throughput is limited primarily by the bandwidth and latency of the attached storage medium.

Advisors: Robert W. Brodersen

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BibTeX citation:

@phdthesis{Camera:EECS-2008-80,
    Author= {Camera, Kevin Brandon},
    Title= {Efficient Programming of Reconfigurable Hardware through Direct Verification},
    School= {EECS Department, University of California, Berkeley},
    Year= {2008},
    Month= {Jun},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-80.html},
    Number= {UCB/EECS-2008-80},
    Abstract= {Reconfigurable hardware devices, such as field-programmable gate arrays (FPGAs), have been shown to achieve greater net throughput and power, energy, and cost efficiency compared to traditional microprocessors in high-performance computing and signal processing applications.  The primary drawback to the use of such devices, however, is the perceived difficulty of the overall programming process, which includes the complete design and verification of the system.

In an attempt alleviate this net system design problem, the approach of <i>direct verification</i> was conceived and implemented on the BEE2 hardware platform.  Direct verification utilizes the resources of the platform to provide variables in the hardware domain, which feature read/write access to data, runtime streaming of data to off-chip storage, and fully automated dynamic assertion checking.  By regulating the design clock, the verification infrastructure can also control the execution of the design under test, both via manual interaction and same-cycle breakpoints triggered by variable assertion failures.  In addition, all this functionality is accessible in the original design environment via a remote network service provided by the software layer of the verification infrastructure, which allows data to be generated and analyzed at the same level of abstraction previously only present during simulation.

The resource requirements to enable direct verification on the BEE2 platform were measured both independently and as part of two real-world design examples.  The base infrastructure was found to occupy about 12% of an XCV2P70 FPGA (8% of which was purely due to the DDR2 memory controller), and the addition of a typical 16-bit variable required 75 logic slices (0.23% of the device) on average.  The operating frequency of the design under test is not severely impacted unless the device utilization approaches 100%, and runtime system throughput is limited primarily by the bandwidth and latency of the attached storage medium.},
}

EndNote citation:

%0 Thesis
%A Camera, Kevin Brandon 
%T Efficient Programming of Reconfigurable Hardware through Direct Verification
%I EECS Department, University of California, Berkeley
%D 2008
%8 June 9
%@ UCB/EECS-2008-80
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-80.html
%F Camera:EECS-2008-80