On-time Network On-Chip: Analysis and Architecture
Dai Bui and Alessandro Pinto and Edward A. Lee
EECS Department, University of California, Berkeley
Technical Report No. UCB/EECS-2009-59
May 8, 2009
http://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-59.pdf
Game, multimedia, consumer and control applications demand low power and high performance computing platforms capable of providing real-time services. Multi-core architectures, supported by on-chip networks, are emerging as scalable solutions to fulfill these requirements. However, the increasing number of concurrent applications running on these platforms, and the time-varying nature of their communications give rise to unpredictable delays.
We propose simple and flexible on-chip protocol and architecture that provide application level communication services with end-to-end timing guarantees. We prove the correctness of our protocol using analytical models and we validate our implementation using detailed simulations.
BibTeX citation:
@techreport{Bui:EECS-2009-59, Author= {Bui, Dai and Pinto, Alessandro and Lee, Edward A.}, Title= {On-time Network On-Chip: Analysis and Architecture}, Year= {2009}, Month= {May}, Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-59.html}, Number= {UCB/EECS-2009-59}, Abstract= {Game, multimedia, consumer and control applications demand low power and high performance computing platforms capable of providing real-time services. Multi-core architectures, supported by on-chip networks, are emerging as scalable solutions to fulfill these requirements. However, the increasing number of concurrent applications running on these platforms, and the time-varying nature of their communications give rise to unpredictable delays. We propose simple and flexible on-chip protocol and architecture that provide application level communication services with end-to-end timing guarantees. We prove the correctness of our protocol using analytical models and we validate our implementation using detailed simulations.}, }
EndNote citation:
%0 Report %A Bui, Dai %A Pinto, Alessandro %A Lee, Edward A. %T On-time Network On-Chip: Analysis and Architecture %I EECS Department, University of California, Berkeley %D 2009 %8 May 8 %@ UCB/EECS-2009-59 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-59.html %F Bui:EECS-2009-59