Kyle Dillon

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2015-104

May 14, 2015

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-104.pdf

Next-generation DDR4 memory has significantly improved performance and energy consumption over previous-generation DDR3 technology. However, this increase in performance and decrease in energy has resulted in a variety of design challenges for peripheral circuitry. This paper focuses on the physical interface for DDR4 memory. The physical interface is the interface over which the processor communicates with the memory.

This paper consists of three main sections: industry analysis, intellectual property strategy, and technical contribution. A market analysis of the memory integrated circuits industry in presented in the industry analysis section. In the IP strategy section, the different options for a physical interface IP are considered and compared. Finally, in the technical contributions section, a research summary of my personal research on DDR4 is presented. Also, a variety of serializer (one of the essential circuit blocks of the physical interface) designs are compared and a preferred design is chosen to be integrated into the physical interface. The other circuit blocks that make up the collaboratively designed physical interface are discussed in greater detail in their respective Capstone reports.

Advisors: Elad Alon and Vladimir Stojanovic

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BibTeX citation:

@mastersthesis{Dillon:EECS-2015-104,
    Author= {Dillon, Kyle},
    Title= {Next Generation Memory Interfaces},
    School= {EECS Department, University of California, Berkeley},
    Year= {2015},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-104.html},
    Number= {UCB/EECS-2015-104},
    Abstract= {Next-generation DDR4 memory has significantly improved performance and energy consumption over previous-generation DDR3 technology.  However, this increase in performance and decrease in energy has resulted in a variety of design challenges for peripheral circuitry. This paper focuses on the physical interface for DDR4 memory.  The physical interface is the interface over which the processor communicates with the memory.

This paper consists of three main sections: industry analysis, intellectual property strategy, and technical contribution. A market analysis of the memory integrated circuits industry in presented in the industry analysis section. In the IP strategy section, the different options for a physical interface IP are considered and compared. Finally, in the technical contributions section, a research summary of my personal research on DDR4 is presented. Also, a variety of serializer (one of the essential circuit blocks of the physical interface) designs are compared and a preferred design is chosen to be integrated into the physical interface. The other circuit blocks that make up the collaboratively designed physical interface are discussed in greater detail in their respective Capstone reports.},
}

EndNote citation:

%0 Thesis
%A Dillon, Kyle 
%T Next Generation Memory Interfaces
%I EECS Department, University of California, Berkeley
%D 2015
%8 May 14
%@ UCB/EECS-2015-104
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-104.html
%F Dillon:EECS-2015-104