Hanh-Phuc Le

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2015-21

May 1, 2015

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-21.pdf

As parallelism increases the number of cores integrated onto a chip, there is a clear need for fully integrated DC-DC converters to enable efficient on-die power management. Due to the availability of high density and low series resistance capacitors in existing CMOS processes, switched-capacitor DC-DC converters have recently gained significant interest as a cost-effective means of enabling such power management functionality.

In this thesis, described are design techniques to implement fully integrated switched- capacitor DC-DC converters with high power density and efficiency. The area required by a fully integrated switched-capacitor DC-DC converter in order to deliver a certain level of power to the load has direct implications on both cost and efficiency, and hence in Chapter 2 a methodology is presented to predict and minimize the losses of such a converter operating at a given power density. Chapter 3 further introduces gate driver and level shifter circuit design strategies to enable topology reconfiguration and hence efficient generation of a wider range of output voltages. In order to demonstrate the possibility of replacing all off-chip PMICs, Chapter 4 presents a battery-connected switched-capacitor DC-DC converter that is able to convert the wide input voltage range from Li-ion battery to an output regulated at ~1V using cascode switches and intermediate voltage rails. The SC converter in Chapter 4 also employs a fast control loop to regulate the output with sub-ns response times.

Measured results from the converters presented in Chapters 3 and 4 match with the analytical prediction and, thus, confirm the design methodology presented in Chapter 2. The 32nm SOI prototype presented in Chapter 3 achieves ~80% efficiency at a power density of ~0.5-1W/mm2 for a 2:1 step-down converter operating from a 2V input and utilizing only standard MOS capacitors. Reconfiguration of the converter’s topology enables it to maintain greater than 70% efficiency for most of the output voltage range from 0.7V to ~1.15V. The 65nm Bulk CMOS prototype discussed in Chapter 4 also utilizes only standard MOS capacitors to regulate the output voltage at ~1V from a ~2.9V-4V input. It achieves ~73% efficiency at 0.19 W/mm² output power density and maintain efficiency above 72% over the whole range of target power density. The sub-ns response control loop maintains lower than 76 mV voltage droop out of a 1V regulated output under a full load step of 0 to 0.253 A/mm² in 50ps.

Given that these results were achieved in a standard CMOS process with no modifications or additions, they illustrate that fully integrated switched-capacitor converters are indeed a promising candidate for low-cost but efficient power management on a per-core or per-functional unit basis. They can possibly replace all the off-chip PMICs and passive components and free up significant PCB area to be used to implement new functions on next-generation mobile devices.

Advisors: Seth R. Sanders and Elad Alon

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BibTeX citation:

@phdthesis{Le:EECS-2015-21,
    Author= {Le, Hanh-Phuc},
    Title= {Design Techniques for Fully Integrated Switched-Capacitor Voltage Regulators},
    School= {EECS Department, University of California, Berkeley},
    Year= {2015},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-21.html},
    Number= {UCB/EECS-2015-21},
    Abstract= {As parallelism increases the number of cores integrated onto a chip, there is a clear need for fully integrated DC-DC converters to enable efficient on-die power management. Due to the availability of high density and low series resistance capacitors in existing CMOS processes, switched-capacitor DC-DC converters have recently gained significant interest as a cost-effective means of enabling such power management functionality.


In this thesis, described are design techniques to implement fully integrated switched- capacitor DC-DC converters with high power density and efficiency. The area required by a fully integrated switched-capacitor DC-DC converter in order to deliver a certain level of power to the load has direct implications on both cost and efficiency, and hence in Chapter 2 a methodology is presented to predict and minimize the losses of such a converter operating at a given power density. Chapter 3 further introduces gate driver and level shifter circuit design strategies to enable topology reconfiguration and hence efficient generation of a wider range of output voltages. In order to demonstrate the possibility of replacing all off-chip PMICs, Chapter 4 presents a battery-connected switched-capacitor DC-DC converter that is able to convert the wide input voltage range from Li-ion battery to an output regulated at ~1V using cascode switches and intermediate voltage rails. The SC converter in Chapter 4 also employs a fast control loop to regulate the output with sub-ns response times.

Measured results from the converters presented in Chapters 3 and 4 match with the analytical prediction and, thus, confirm the design methodology presented in Chapter 2. The 32nm SOI prototype presented in Chapter 3 achieves ~80% efficiency at a power density of ~0.5-1W/mm2 for a 2:1 step-down converter operating from a 2V input and utilizing only standard MOS capacitors. Reconfiguration of the converter’s topology enables it to maintain greater than 70% efficiency for most of the output voltage range from 0.7V to ~1.15V. The 65nm Bulk CMOS prototype discussed in Chapter 4 also utilizes only standard MOS capacitors to regulate the output voltage at ~1V from a ~2.9V-4V input. It achieves ~73% efficiency at 0.19 W/mm<sup>2</sup> output power density and maintain efficiency above 72% over the whole range of target power density. The sub-ns response control loop maintains lower than 76 mV voltage droop out of a 1V regulated output under a full load step of 0 to 0.253 A/mm<sup>2</sup> in 50ps.

Given that these results were achieved in a standard CMOS process with no modifications or additions, they illustrate that fully integrated switched-capacitor converters are indeed a promising candidate for low-cost but efficient power management on a per-core or per-functional unit basis. They can possibly replace all the off-chip PMICs and passive components and free up significant PCB area to be used to implement new functions on next-generation mobile devices.},
}

EndNote citation:

%0 Thesis
%A Le, Hanh-Phuc 
%T Design Techniques for Fully Integrated Switched-Capacitor Voltage Regulators
%I EECS Department, University of California, Berkeley
%D 2015
%8 May 1
%@ UCB/EECS-2015-21
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-21.html
%F Le:EECS-2015-21