CMOS and Memristor Technologies for Neuromorphic Computing Applications

THIS REPORT HAS BEEN WITHDRAWN

Jeff Sun

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2015-218
December 1, 2015

In this work, I present a CMOS implementation of a neuromorphic system that aims to mimic the behavior of biological neurons and synapses in the human brain. The synapse is modeled with a memristor-resistor voltage divider, while the neuron-emulating circuit (“CMOS Neuron”) comprises transistors and capacitors. The input aggregation and output firing characteristics of a CMOS Neuron are based on observations from studies in neuroscience, and achieved using both analog and digital circuit design principles. The important Spike Timing Dependent Plasticity (STDP) learning scheme is explored in detail, and a simple adaptive learning experiment is performed to demonstrate the CMOS Neuron’s potential for future artificial intelligence applications.

Advisor: Tsu-Jae King Liu

Author Comments: see http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-219.html