Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language

Stephen Twigg

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2015-256

December 18, 2015

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http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/Archive/EECS-2015-256.pdf

Using hardware generators to produce components for modern SoCs enables rapid design space exploration. Embedding these hardware generators in a high-level programming language allows for simpler code, more expressive generators, and correspondingly better quality of results. This thesis describes the use of Chisel (Constructing Hardware in a Scala Embedded Language) to construct an FFT generator. The parametrized generator demonstrates automatic parameter-dependent test generation and seamless system integration. An analysis of FFT scheduling is performed to show how various mathematical properties of the Cooley-Tukey FFT decomposition may be exploited to simplify needed hardware while assuring conflict-free bank accesses for every operation. The resulting circuit throughput, energy, and area are shown to be better than or on par with other FFT generators.

Advisors: John Wawrzynek

BibTeX citation:

@mastersthesis{Twigg:EECS-2015-256,
    Author= {Twigg, Stephen},
    Editor= {Wawrzynek, John and Nikolic, Borivoje},
    Title= {Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language},
    School= {EECS Department, University of California, Berkeley},
    Year= {2015},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-256.html},
    Number= {UCB/EECS-2015-256},
    Abstract= {Using hardware generators to produce components for modern SoCs enables rapid design space exploration. Embedding these hardware generators in a high-level programming language allows for simpler code, more expressive generators, and correspondingly better quality of results. This thesis describes the use of Chisel (Constructing Hardware in a Scala Embedded Language) to construct an FFT generator. The parametrized generator demonstrates automatic parameter-dependent test generation and seamless system integration. An analysis of FFT scheduling is performed to show how various mathematical properties of the Cooley-Tukey FFT decomposition may be exploited to simplify needed hardware while assuring conflict-free bank accesses for every operation. The resulting circuit throughput, energy, and area are shown to be better than or on par with other FFT generators.},
}

EndNote citation:

%0 Thesis
%A Twigg, Stephen 
%E Wawrzynek, John 
%E Nikolic, Borivoje 
%T Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language
%I EECS Department, University of California, Berkeley
%D 2015
%8 December 18
%@ UCB/EECS-2015-256
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-256.html
%F Twigg:EECS-2015-256