The Rocket Chip Generator

Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2016-17
April 15, 2016

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf

Rocket Chip is an open-source Sysem-on-Chip design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. Rocket Chip generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM). For SoC designers interested in utilizing heterogeneous specialization for added efficiency gains, Rocket Chip supports the integration of custom accelerators in the form of instruction set extensions, coprocessors, or fully independent novel cores. Rocket Chip has been taped out (manufactured) eleven times, and yielded functional silicon prototypes capable of booting Linux.


BibTeX citation:

@techreport{Asanović:EECS-2016-17,
    Author = {Asanović, Krste and Avizienis, Rimas and Bachrach, Jonathan and Beamer, Scott and Biancolin, David and Celio, Christopher and Cook, Henry and Dabbelt, Daniel and Hauser, John and Izraelevitz, Adam and Karandikar, Sagar and Keller, Ben and Kim, Donggyu and Koenig, John and Lee, Yunsup and Love, Eric and Maas, Martin and Magyar, Albert and Mao, Howard and Moreto, Miquel and Ou, Albert and Patterson, David A. and Richards, Brian and Schmidt, Colin and Twigg, Stephen and Vo, Huy and Waterman, Andrew},
    Title = {The Rocket Chip Generator},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2016},
    Month = {Apr},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html},
    Number = {UCB/EECS-2016-17},
    Abstract = {Rocket Chip is an open-source Sysem-on-Chip design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. Rocket Chip generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM). For SoC designers interested in utilizing heterogeneous specialization for added efficiency gains, Rocket Chip supports the integration of custom accelerators in the form of instruction set extensions, coprocessors, or fully independent novel cores. Rocket Chip has been taped out (manufactured) eleven times, and yielded functional silicon prototypes capable of booting Linux.}
}

EndNote citation:

%0 Report
%A Asanović, Krste
%A Avizienis, Rimas
%A Bachrach, Jonathan
%A Beamer, Scott
%A Biancolin, David
%A Celio, Christopher
%A Cook, Henry
%A Dabbelt, Daniel
%A Hauser, John
%A Izraelevitz, Adam
%A Karandikar, Sagar
%A Keller, Ben
%A Kim, Donggyu
%A Koenig, John
%A Lee, Yunsup
%A Love, Eric
%A Maas, Martin
%A Magyar, Albert
%A Mao, Howard
%A Moreto, Miquel
%A Ou, Albert
%A Patterson, David A.
%A Richards, Brian
%A Schmidt, Colin
%A Twigg, Stephen
%A Vo, Huy
%A Waterman, Andrew
%T The Rocket Chip Generator
%I EECS Department, University of California, Berkeley
%D 2016
%8 April 15
%@ UCB/EECS-2016-17
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html
%F Asanović:EECS-2016-17