Accelerator Synthesis and Integration for CPU+FPGA Systems

Shaoyi Cheng

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2016-205
December 15, 2016

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-205.pdf

Advisor: John Wawrzynek


BibTeX citation:

@phdthesis{Cheng:EECS-2016-205,
    Author = {Cheng, Shaoyi},
    Title = {Accelerator Synthesis and Integration for CPU+FPGA Systems},
    School = {EECS Department, University of California, Berkeley},
    Year = {2016},
    Month = {Dec},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-205.html},
    Number = {UCB/EECS-2016-205}
}

EndNote citation:

%0 Thesis
%A Cheng, Shaoyi
%T Accelerator Synthesis and Integration for CPU+FPGA Systems
%I EECS Department, University of California, Berkeley
%D 2016
%8 December 15
%@ UCB/EECS-2016-205
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-205.html
%F Cheng:EECS-2016-205