Gary Choi

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2017-108

May 16, 2017

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-108.pdf

Using multiple cores on SoC’s are a well accepted solution to improving performance without using as much power as scaling up frequency but each core is a digital circuit that needs to be driven by a clock. Global clock distribution networks are responsible for delivering a reference clock signal to local clock generators that generate local clocks for each core. Current clock distribution and generation circuits tend to consume a lot of power and don’t have a set phase relationship, creating a need for synchronizers that inherently have some latency that limits throughput. This work aims to present a self-adjustable clock generator that multiplies the reference frequency to allow for slower references, which reduces power in clock distribution, and periodically injects the reference frequency to better establish a phase relation between the reference and output frequency. The main focus of the design is on a multiplying delay-locked loop whose frequency is managed by a digital control circuit. The circuit generates 16 phases of 2GHz using a 500 MHz injected reference signal. The injection allows the phase error to reset with every injection.

Advisors: Borivoje Nikolic

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BibTeX citation:

@mastersthesis{Choi:EECS-2017-108,
    Author= {Choi, Gary},
    Editor= {Nikolic, Borivoje},
    Title= {A Multiplying Delay-Locked Loop For A Self-Adjustable Clock Generator},
    School= {EECS Department, University of California, Berkeley},
    Year= {2017},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-108.html},
    Number= {UCB/EECS-2017-108},
    Abstract= {Using multiple cores on SoC’s are a well accepted solution to improving performance without using as much power as scaling up frequency but each core is a digital circuit that needs to be driven by a clock. Global clock distribution networks are responsible for delivering a reference clock signal to local clock generators that generate local clocks for each core. Current clock distribution and generation circuits tend to consume a lot of power and don’t have a set phase relationship, creating a need for synchronizers that inherently have some latency that limits throughput. This work aims to present a self-adjustable clock generator that multiplies the reference frequency to allow for slower references, which reduces power in clock distribution, and periodically injects the reference frequency to better establish a phase relation between the reference and output frequency. The main focus of the design is on a multiplying delay-locked loop whose frequency is managed by a digital control circuit. The circuit generates 16 phases of 2GHz using a 500 MHz injected reference signal. The injection allows the phase error to reset with every injection.},
}

EndNote citation:

%0 Thesis
%A Choi, Gary 
%E Nikolic, Borivoje 
%T A Multiplying Delay-Locked Loop For A Self-Adjustable Clock Generator
%I EECS Department, University of California, Berkeley
%D 2017
%8 May 16
%@ UCB/EECS-2017-108
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-108.html
%F Choi:EECS-2017-108