High-Frequency Clock Distribution Methods in Digital Integrated Circuits

Sajjad Moazeni

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2017-116
June 6, 2017

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-116.pdf

This paper provides a comparative study of the proposed global clock distribution methods for high-speed digital integrated circuits. Both non-networked and distributed schemes such as travelling and standing wave clock distributions have been reviewed. Performance metrics are described and qualitatively discussed and non-networked approaches were simulated in a low-power 65nm CMOS process.


BibTeX citation:

@techreport{Moazeni:EECS-2017-116,
    Author = {Moazeni, Sajjad},
    Title = {High-Frequency Clock Distribution Methods in Digital Integrated Circuits},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2017},
    Month = {Jun},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-116.html},
    Number = {UCB/EECS-2017-116},
    Abstract = {This paper provides a comparative study of the proposed global clock distribution methods for high-speed digital integrated circuits. Both non-networked and distributed schemes such as travelling and standing wave clock distributions have been reviewed. Performance metrics are described and qualitatively discussed and non-networked approaches were simulated in a low-power 65nm CMOS process.}
}

EndNote citation:

%0 Report
%A Moazeni, Sajjad
%T High-Frequency Clock Distribution Methods in Digital Integrated Circuits
%I EECS Department, University of California, Berkeley
%D 2017
%8 June 6
%@ UCB/EECS-2017-116
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-116.html
%F Moazeni:EECS-2017-116