Vladimir Stojanovic and liheng zhu

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2017-72

May 12, 2017

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-72.pdf

For our project, High-Speed Data Link, we are trying to implement a serial communication link that can operate at ~25Gb/s through a noisy channel. We decided to build a parameterized library to allow individual user to set up his/her own parameters according to the project specifications and requirements. So far, we have decided that there is a five-stage project plan for this year. First we need to familiarize ourselves with the high-level architecture of this high speed link model in Matlab as well as the simulation and related architectural modifications. Secondly, we need to translate our architecture into the hardware description language, most likely Verilog or Verilog-A using some circuit modeling tools like Cadence, etc. Thirdly, we need to implement the schematic of our high-speed link circuits and fourthly, finish the layout of this schematic, which means we need to map and place and route the circuits logic to real silicon. The final phase of the project should be the final verification of the project to make sure it is a clean design that is free of bugs.

Advisors: Vladimir Stojanovic

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BibTeX citation:

@mastersthesis{Stojanovic:EECS-2017-72,
    Author= {Stojanovic, Vladimir and zhu, liheng},
    Title= {High Speed Data Link},
    School= {EECS Department, University of California, Berkeley},
    Year= {2017},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-72.html},
    Number= {UCB/EECS-2017-72},
    Abstract= {For our project, High-Speed Data Link, we are trying to implement a serial communication link that can operate at ~25Gb/s through a noisy channel. We decided to build a parameterized library to allow individual user to set up his/her own parameters
according to the project specifications and requirements. So far, we have decided that there is a five-stage project plan for this year. First we need to familiarize ourselves with the high-level architecture of this high speed link model in Matlab as well as the simulation and related architectural modifications. Secondly, we need to translate our architecture into the hardware description language, most likely Verilog or Verilog-A using some circuit modeling tools like Cadence, etc. Thirdly, we need to implement the schematic of our
high-speed link circuits and fourthly, finish the layout of this schematic, which means we need to map and place and route the circuits logic to real silicon. The final phase of the project should be the final verification of the project to make sure it is a clean design that is free of bugs.},
}

EndNote citation:

%0 Thesis
%A Stojanovic, Vladimir 
%A zhu, liheng 
%T High Speed Data Link
%I EECS Department, University of California, Berkeley
%D 2017
%8 May 12
%@ UCB/EECS-2017-72
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-72.html
%F Stojanovic:EECS-2017-72