Ying Qiao

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2018-148

December 1, 2018

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-148.pdf

It is widely recognized that in nano-scale CMOS technology variation in the manufacturing process has emerged as a fundamental challenge to IC design. While foundries are working hard to mitigate process variability, the design houses are asking for accurate and appropriate models to handle statistical circuit performance evaluation. To accurately represent the process and device variability, it is essential to incorporate the variability during the extraction and calibration phase of compact transistor models. In addition, these compact transistor models require customized test structure designs as well as proper statistical characterization procedures. Conventional statistical compact model characterization methodologies require special single transistor, direct-access test arrays, or virtual measurements from physical simulation data; moreover, these models do not include rigorous statistical model parameter selection criteria. Our proposed variability-aware compact transistor models can enable statistically optimized designs by capturing device variations in a concise, yet physically accurate way, and they are relatively easy to integrate with existing CAD tool flow. In this work, we have electrical measurements from carefully designed SRAM array test structures with bit transistor access, fabricated using a collaborating foundry’s 28nm FDSOI technology. Stepwise parameter selection is combined with sequential extractions of statistical compact model parameters upon foundry-provided nominal compact model cards. These nominal models are trusted as they have been tested extensively and used during the test structure design. Our characterization methodology selects an optimal statistical model parameter set that can be reliability extracted with the given measurement data. With further data from imaging ROIC test array, we are able to explore the linear spatial propagation of variance method to extract the variability in the compact model parameters with hierarchical models. We have also built a customized Monte Carlo (MC) simulation platform to utilize these compact transistor models in the statistical IC design flow. Different statistical model parameters can be specified prior to the MC simulation within the scripted wrapper of standard SPICE-based simulators. We further exploit the statistical structure of the extracted parameters in order to capture the nonlinear correlations and the non-Gaussian distributions through mixture of Gaussian distributions. The goal is to demonstrate that significant non-normality in the measured data can be captured by our simplified model. Such non-normality is often evident at the tails of the performance distributions, and capturing that is necessary for the statistical modeling of inherently high-yielding IC designs.

Advisors: Costas J. Spanos

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BibTeX citation:

@phdthesis{Qiao:EECS-2018-148,
    Author= {Qiao, Ying},
    Editor= {Spanos, Costas J. and Nikolic, Borivoje},
    Title= {Variability-Aware Compact Modeling of Nano-scale Technologies with Customized Test Structure Designs},
    School= {EECS Department, University of California, Berkeley},
    Year= {2018},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-148.html},
    Number= {UCB/EECS-2018-148},
    Abstract= {It is widely recognized that in nano-scale CMOS technology variation in the
manufacturing process has emerged as a fundamental challenge to IC design. While
foundries are working hard to mitigate process variability, the design houses are
asking for accurate and appropriate models to handle statistical circuit performance
evaluation. To accurately represent the process and device variability, it is essential
to incorporate the variability during the extraction and calibration phase of compact
transistor models. In addition, these compact transistor models require customized
test structure designs as well as proper statistical characterization procedures.
Conventional statistical compact model characterization methodologies require
special single transistor, direct-access test arrays, or virtual measurements from
physical simulation data; moreover, these models do not include rigorous statistical
model parameter selection criteria.
Our proposed variability-aware compact transistor models can enable
statistically optimized designs by capturing device variations in a concise, yet
physically accurate way, and they are relatively easy to integrate with existing CAD
tool flow. In this work, we have electrical measurements from carefully designed
SRAM array test structures with bit transistor access, fabricated using a
collaborating foundry’s 28nm FDSOI technology. Stepwise parameter selection is
combined with sequential extractions of statistical compact model parameters upon
foundry-provided nominal compact model cards. These nominal models are trusted
as they have been tested extensively and used during the test structure design.
Our characterization methodology selects an optimal statistical model
parameter set that can be reliability extracted with the given measurement data.
With further data from imaging ROIC test array, we are able to explore the linear
spatial propagation of variance method to extract the variability in the compact
model parameters with hierarchical models.
We have also built a customized Monte Carlo (MC) simulation platform to
utilize these compact transistor models in the statistical IC design flow. Different
statistical model parameters can be specified prior to the MC simulation within the
scripted wrapper of standard SPICE-based simulators. We further exploit the
statistical structure of the extracted parameters in order to capture the nonlinear
correlations and the non-Gaussian distributions through mixture of Gaussian
distributions. The goal is to demonstrate that significant non-normality in the
measured data can be captured by our simplified model. Such non-normality is
often evident at the tails of the performance distributions, and capturing that is
necessary for the statistical modeling of inherently high-yielding IC designs.},
}

EndNote citation:

%0 Thesis
%A Qiao, Ying 
%E Spanos, Costas J. 
%E Nikolic, Borivoje 
%T Variability-Aware Compact Modeling of Nano-scale Technologies with Customized Test Structure Designs
%I EECS Department, University of California, Berkeley
%D 2018
%8 December 1
%@ UCB/EECS-2018-148
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-148.html
%F Qiao:EECS-2018-148