A. Gokcen Mahmutoglu and Xufeng Wang and Jaijeet Roychowdhury

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2018-89

July 4, 2018

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-89.pdf

We present software tools, VAPP and VALint, for the development of new Verilog-A compact models and also for applications involving existing models. VAPP, the Berkeley Verilog-A Parser and Processor, translates Verilog-A device models into executable and accessible model code. VALint is a graphical code quality checking tool. By virtue of its intuitive syntax for creating compact device models, Verilog-A has come to be used as the standard compact modeling language in the electrical engineering community. However, the high-level language constructs of Verilog-A necessitate the translation of device model code into a lower-level model description format before it can be used in simulations. VAPP runs in MATLAB/Octave, takes a Verilog-A model as input and, by default, generates executable model code in the open ModSpec format complete with symbolically computed derivatives. VAPP features a modular software architecture which can be easily modified and extended to be used with different model description formats and target programming languages. Together with the Berkeley Model and Algorithm Prototyping Platform (MAPP), VAPP offers a powerful framework for testing, debugging and analyzing compact device models. VALint assists model developers in writing clean Verilog-A code by checking models for common mistakes and bad Verilog-A practices. VALint implements rules for best Verilog-A modeling practices accumulated over the years by leading industry experts. VAPP and VALint are freely available and released as open source code.

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BibTeX citation:

@techreport{Mahmutoglu:EECS-2018-89,
    Author= {Mahmutoglu, A. Gokcen and Wang, Xufeng and Roychowdhury, Jaijeet},
    Title= {New Generation Verilog-A Model Development Tools: VAPP and VALint},
    Year= {2018},
    Month= {Jul},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-89.html},
    Number= {UCB/EECS-2018-89},
    Abstract= {We present software tools, VAPP and VALint, for the development of new Verilog-A compact models and also for applications involving existing models. 
VAPP, the Berkeley Verilog-A Parser and Processor, translates Verilog-A device models into executable and accessible model code. 
VALint is a graphical code quality checking tool.
By virtue of its intuitive syntax for creating compact device models, Verilog-A has come to be used as the standard compact modeling language in the electrical engineering community. 
However, the high-level language constructs of Verilog-A necessitate the translation of device model code into a lower-level model description format before it can be used in simulations.
VAPP runs in MATLAB/Octave, takes a Verilog-A model as input and, by default, generates executable model code in the open ModSpec format complete with symbolically computed derivatives.
VAPP features a modular software architecture which can be easily modified and extended to be used with different model description formats and target programming languages.
Together with the Berkeley Model and Algorithm Prototyping Platform (MAPP), VAPP offers a powerful framework for testing, debugging and analyzing compact device models.
VALint assists model developers in writing clean Verilog-A code by checking models for common mistakes and bad Verilog-A practices.
VALint implements rules for best Verilog-A modeling practices accumulated over the years by leading industry experts.
VAPP and VALint are freely available and released as open source code.},
}

EndNote citation:

%0 Report
%A Mahmutoglu, A. Gokcen 
%A Wang, Xufeng 
%A Roychowdhury, Jaijeet 
%T New Generation Verilog-A Model Development Tools: VAPP and VALint
%I EECS Department, University of California, Berkeley
%D 2018
%8 July 4
%@ UCB/EECS-2018-89
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-89.html
%F Mahmutoglu:EECS-2018-89