Jaeduk Han

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2019-143

December 1, 2019

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.pdf

The continual expansion of Internet connectivity has raised data traffic substantially, increasing demands on high-bandwidth wireline communication systems. In contrast to the rapid increase in bandwidth that will be necessary, the allowable power consumption of high-speed transceivers remains relatively constant. Specifically, assuming the same total power budget as current designs, transceivers operating in the range of 50-60Gb/s must achieve 3-5pJ/bit efficiency to remain within the current total power window. To address these trends and challenges, this thesis first reports a 60Gb/s receiver frontend in a 65nm CMOS process. Current integration combined with a cascode gate-voltage bias technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. The addition of interleaved, offset-canceled deserializing samplers addresses the high gain requirement of adaptive error-samplers. The prototype 65nm CMOS receiver operates at 60Gb/s, consuming 173mW from 1.2V and 1.0V supplies. To enhance the productivity and quality of the receive equalizer design by capturing the parasitic loading and wiring capacitance promptly and precisely, an automated flow that generates the equalizer schematic and layout from target specifications and technology parameters is developed. Utilizing the Berkeley Analog Generator, the equalizer generation flow is scripted, executed, and iterated automatically to produce an optimal design that meets for a given configuration. In addition to presenting the equalizer design, the thesis also introduces a new baud-rate CDR scheme that leverages the current integration frontend and phase dithering. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset. The resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The implemented 65nm CMOS transceiver operates at 60Gb/s with an eye-opening of 30% UI and consumes 288mW while equalizing 21dB of loss at 30GHz over a 0.7m Twinax cable.

Advisors: Elad Alon

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BibTeX citation:

@phdthesis{Han:EECS-2019-143,
    Author= {Han, Jaeduk},
    Title= {Design and Automatic Generation of 60Gb/s Wireline Transceivers},
    School= {EECS Department, University of California, Berkeley},
    Year= {2019},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.html},
    Number= {UCB/EECS-2019-143},
    Abstract= {The continual expansion of Internet connectivity has raised data traffic substantially, increasing demands on high-bandwidth wireline communication systems. In contrast to the rapid increase in bandwidth that will be necessary, the allowable power consumption of high-speed transceivers remains relatively constant. Specifically, assuming the same total power budget as current designs, transceivers operating in the range of 50-60Gb/s must achieve 3-5pJ/bit efficiency to remain within the current total power window.
To address these trends and challenges, this thesis first reports a 60Gb/s receiver frontend in a 65nm CMOS process. Current integration combined with a cascode gate-voltage bias technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. The addition of interleaved, offset-canceled deserializing samplers addresses the high gain requirement of adaptive error-samplers. The prototype 65nm CMOS receiver operates at 60Gb/s, consuming 173mW from 1.2V and 1.0V supplies.
To enhance the productivity and quality of the receive equalizer design by capturing the parasitic loading and wiring capacitance promptly and precisely, an automated flow that generates the equalizer schematic and layout from target specifications and technology parameters is developed. Utilizing the Berkeley Analog Generator, the equalizer generation flow is scripted, executed, and iterated automatically to produce an optimal design that meets for a given configuration.
In addition to presenting the equalizer design, the thesis also introduces a new baud-rate CDR scheme that leverages the current integration frontend and phase dithering. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset. The resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The implemented 65nm CMOS transceiver operates at 60Gb/s with an eye-opening of 30% UI and consumes 288mW while equalizing 21dB of loss at 30GHz over a 0.7m Twinax cable.},
}

EndNote citation:

%0 Thesis
%A Han, Jaeduk 
%T Design and Automatic Generation of 60Gb/s Wireline Transceivers
%I EECS Department, University of California, Berkeley
%D 2019
%8 December 1
%@ UCB/EECS-2019-143
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-143.html
%F Han:EECS-2019-143