Adam Izraelevitz

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2019-168

December 5, 2019

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-168.pdf

Emerging applications from the edge to the cloud are constantly increasing demand for energy efficient and performant computation. While specialized hardware can meet these power and performance goals, the high non-reoccurring engineering (NRE) costs of designing, testing, and verifying custom hardware severely hinders its supply. Hardware construction languages such as Chisel enable hardware designers to write parameterized hardware libraries which increase design reuse by turning NRE effort into reusable solutions for future specialized chips. This thesis introduces FIRRTL, Chisel’s hardware compiler framework, which enables automatic and custom RTL-transformations including logic optimization and design instrumentation. In addition, this thesis proposes an aspect-oriented-inspired paradigm, Colla-Gen, as a mechanism to improve design collateral reuse (e.g. physical design floorplanning or verification instrumentation), which forms another large portion of chip NRE costs.

Advisors: Krste Asanović and Jonathan Bachrach

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BibTeX citation:

@phdthesis{Izraelevitz:EECS-2019-168,
    Author= {Izraelevitz, Adam},
    Editor= {Bachrach, Jonathan and Asanović, Krste and Schleicher, Simon and Ragan-Kelley, Jonathan},
    Title= {Unlocking Design Reuse with Hardware Compiler Frameworks},
    School= {EECS Department, University of California, Berkeley},
    Year= {2019},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-168.html},
    Number= {UCB/EECS-2019-168},
    Abstract= {Emerging applications from the edge to the cloud are constantly increasing demand for energy efficient and performant computation. While specialized hardware can meet these power and performance goals, the high non-reoccurring engineering (NRE) costs of designing, testing, and verifying custom hardware severely hinders its supply. Hardware construction languages such as Chisel enable hardware designers to write parameterized hardware libraries which increase design reuse by turning NRE effort into reusable solutions for future specialized chips. This thesis introduces FIRRTL, Chisel’s hardware compiler framework, which enables automatic and custom RTL-transformations including logic optimization and design instrumentation. In addition, this thesis proposes an aspect-oriented-inspired paradigm, Colla-Gen, as a mechanism to improve design collateral reuse (e.g. physical design floorplanning or verification instrumentation), which forms another large portion of chip NRE costs.},
}

EndNote citation:

%0 Thesis
%A Izraelevitz, Adam 
%E Bachrach, Jonathan 
%E Asanović, Krste 
%E Schleicher, Simon 
%E Ragan-Kelley, Jonathan 
%T Unlocking Design Reuse with Hardware Compiler Frameworks
%I EECS Department, University of California, Berkeley
%D 2019
%8 December 5
%@ UCB/EECS-2019-168
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-168.html
%F Izraelevitz:EECS-2019-168