FPGA-Accelerated Evaluation and Verification of RTL Designs

Donggyu Kim

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2019-57
May 17, 2019

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-57.pdf

Advisor: Krste Asanović and Jonathan Bachrach


BibTeX citation:

@phdthesis{Kim:EECS-2019-57,
    Author = {Kim, Donggyu},
    Title = {FPGA-Accelerated Evaluation and Verification of RTL Designs},
    School = {EECS Department, University of California, Berkeley},
    Year = {2019},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-57.html},
    Number = {UCB/EECS-2019-57}
}

EndNote citation:

%0 Thesis
%A Kim, Donggyu
%T FPGA-Accelerated Evaluation and Verification of RTL Designs
%I EECS Department, University of California, Berkeley
%D 2019
%8 May 17
%@ UCB/EECS-2019-57
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-57.html
%F Kim:EECS-2019-57