RF Transmitter Design for Large Antenna Array Applications
Pengpeng Lu
EECS Department, University of California, Berkeley
Technical Report No. UCB/EECS-2020-191
December 1, 2020
http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-191.pdf
Recent advances in wireless technologies have enabled fast increase of mobile data traffic. In fact, mobile data traffic has grown 18-fold over the past 5 years. The rapid growing demand imposes a big near-far problem on our wireless network. Beamforming technique provides an opportunity to efficiently solve the near-far problem, by combining elements in an antenna array in such a way that signals at particular angles experience constructive interference while others experience destructive interference.
This thesis focuses on the design of energy-efficient RF transmitters for large antenna array applications. In order to be energy-efficient, we should minimize the overhead power consumption. It makes the design challenging while minimizing out-of-band emissions and supporting multiple/reconfigurable bands as well as programmability in terms of performance (i.e., output power, noise figure, resolution, bandwidth, etc.), since any fixed frequency bandpass filters should be eliminated.
To address these challenges, a mixer-last TX architecture is proposed, which uses current DACs to deliver charge directly to the 50 Ohm output RF load. Out-of-band emissions are reduced by digital oversampling, and the charging operation of a baseband capacitor.
Using the proposed transmitter architectures, two chips were implemented. The first chip was fabricated in TSMC's 65nm CMOS technology. With a peak output power of 5.1dBm, the first chip consumes 49.2 mW and the measured noise floor at 40MHz offset is -155dBc/Hz. Realizing it is impossible to build a single transmitter that is power efficient under all applications, we developed a generator for our proposed TX architecture using Berkeley Analog Generator (BAG) framework. A generator captures the design methodology and is process portable. It could significantly lower the design cost so that different transmitters that are efficient for different design specifications can be generated.The second chip was generated by the generator and was fabricated in TSMC's 16nm CMOS technology. It consumes 5.14 mW at peak output power of -19.6 dBm. Compared with the first 65nm prototype, it is more power efficient in the output power range of less than -4 dBm.
Advisors: Elad Alon
BibTeX citation:
@phdthesis{Lu:EECS-2020-191,
Author= {Lu, Pengpeng},
Title= {RF Transmitter Design for Large Antenna Array Applications},
School= {EECS Department, University of California, Berkeley},
Year= {2020},
Month= {Dec},
Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-191.html},
Number= {UCB/EECS-2020-191},
Abstract= {Recent advances in wireless technologies have enabled fast increase of mobile data traffic. In fact, mobile data traffic has grown 18-fold over the past 5 years. The rapid growing demand imposes a big near-far problem on our wireless network. Beamforming technique provides an opportunity to efficiently solve the near-far problem, by combining elements in an antenna array in such a way that signals at particular angles experience constructive interference while others experience destructive interference.
This thesis focuses on the design of energy-efficient RF transmitters for large antenna array applications. In order to be energy-efficient, we should minimize the overhead power consumption. It makes the design challenging while minimizing out-of-band emissions and supporting multiple/reconfigurable bands as well as programmability in terms of performance (i.e., output power, noise figure, resolution, bandwidth, etc.), since any fixed frequency bandpass filters should be eliminated.
To address these challenges, a mixer-last TX architecture is proposed, which uses current DACs to deliver charge directly to the 50 Ohm output RF load. Out-of-band emissions are reduced by digital oversampling, and the charging operation of a baseband capacitor.
Using the proposed transmitter architectures, two chips were implemented. The first chip was fabricated in TSMC's 65nm CMOS technology. With a peak output power of 5.1dBm, the first chip consumes 49.2 mW and the measured noise floor at 40MHz offset is -155dBc/Hz. Realizing it is impossible to build a single transmitter that is power efficient under all applications, we developed a generator for our proposed TX architecture using Berkeley Analog Generator (BAG) framework. A generator captures the design methodology and is process portable. It could significantly lower the design cost so that different transmitters that are efficient for different design specifications can be generated.The second chip was generated by the generator and was fabricated in TSMC's 16nm CMOS technology. It consumes 5.14 mW at peak output power of -19.6 dBm. Compared with the first 65nm prototype, it is more power efficient in the output power range of less than -4 dBm.},
}
EndNote citation:
%0 Thesis %A Lu, Pengpeng %T RF Transmitter Design for Large Antenna Array Applications %I EECS Department, University of California, Berkeley %D 2020 %8 December 1 %@ UCB/EECS-2020-191 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-191.html %F Lu:EECS-2020-191