Design for Performance and Reliability in Advanced CMOS Structures
Fei Ding
EECS Department, University of California, Berkeley
Technical Report No. UCB/EECS-2020-41
May 5, 2020
http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-41.pdf
In the past few decades, the central theme of the electronics industry is to increase the transistor density by reducing the transistor area, as required by the Moore's Law. The paradigm shift from the planar CMOS technology to the FinFET technology sustains this area scaling trend into sub-20nm era. The enhancement in the transistor electrostatics in the FinFET enables further scaling of the gate length and hence the contacted poly pitch (CPP). Meanwhile, the quest for area scaling also comes from the width (or fin pitch) and height dimensions. By reducing the fin pitch and increasing the fin height, the current density of the FinFET can be improved. Consequently, circuit designers can use fewer fins to meet the same current requirement and save area simultaneously, a scheme commonly referred to as "fin-depopulation." However, the aforementioned approaches start to show diminishing returns and meet excessive fabrication challenges. To further improve the current density and reduce the area, novel channel materials with high mobility (e.g., SiGe) and/or new structures with even better electrostatics (e.g., Inserted-oxide FinFET (iFinFET), Gate-All-Around FET, Nanosheet FET) are projected to be used in the future. In the first part of the talk, the performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si0.9Ge0.1) channel region is evaluated using 3-D TCAD simulations. It is shown that the hetero-channel design provides for larger current density while maintaining comparable electrostatic integrity as the conventional Si FinFET design due to the valence band (VB) offset between SiGe and Si. Secondly, a scheme for controllably adjusting transistor drive strength in iFinFET technology is proposed, to enable cell ratio tuning for a minimally sized six-transistor SRAM (6-T Static Random Access Memory) cell. It is demonstrated, via 3-D TCAD simulation, that this scheme can reduce the minimum cell operating voltage (V_{min}) and facilitate further cell area scaling. Lastly, as the transistor area continues to shrink, self-heating effects of these small-geometry transistors have been of great concern as it limits the electrical performance and degrades the reliability of transistors. It is important to understand how self-heating may be for these new transistor structures as compared to FinFETs. The performance of advanced transistor structures (i.e., FinFET, Gate-All-Around FET, and Nanosheet FET) is simulated and compared under the constraints of the self-heating. An optimization guideline for nanosheet FETs is also proposed based on the study of various design parameters on the self-heating effects.
Advisors: Tsu-Jae King Liu
BibTeX citation:
@phdthesis{Ding:EECS-2020-41,
Author= {Ding, Fei},
Title= {Design for Performance and Reliability in Advanced CMOS Structures},
School= {EECS Department, University of California, Berkeley},
Year= {2020},
Month= {May},
Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-41.html},
Number= {UCB/EECS-2020-41},
Abstract= { In the past few decades, the central theme of the electronics industry is to increase the transistor density by reducing the transistor area, as required by the Moore's Law. The paradigm shift from the planar CMOS technology to the FinFET technology sustains this area scaling trend into sub-20nm era. The enhancement in the transistor electrostatics in the FinFET enables further scaling of the gate length and hence the contacted poly pitch (CPP). Meanwhile, the quest for area scaling also comes from the width (or fin pitch) and height dimensions. By reducing the fin pitch and increasing the fin height, the current density of the FinFET can be improved. Consequently, circuit designers can use fewer fins to meet the same current requirement and save area simultaneously, a scheme commonly referred to as "fin-depopulation." However, the aforementioned approaches start to show diminishing returns and meet excessive fabrication challenges. To further improve the current density and reduce the area, novel channel materials with high mobility (e.g., SiGe) and/or new structures with even better electrostatics (e.g., Inserted-oxide FinFET (iFinFET), Gate-All-Around FET, Nanosheet FET) are projected to be used in the future.
In the first part of the talk, the performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si0.9Ge0.1) channel region is evaluated using 3-D TCAD simulations. It is shown that the hetero-channel design provides for larger current density while maintaining comparable electrostatic integrity as the conventional Si FinFET design due to the valence band (VB) offset between SiGe and Si.
Secondly, a scheme for controllably adjusting transistor drive strength in iFinFET technology is proposed, to enable cell ratio tuning for a minimally sized six-transistor SRAM (6-T Static Random Access Memory) cell. It is demonstrated, via 3-D TCAD simulation, that this scheme can reduce the minimum cell operating voltage (V_{min}) and facilitate further cell area scaling.
Lastly, as the transistor area continues to shrink, self-heating effects of these small-geometry transistors have been of great concern as it limits the electrical performance and degrades the reliability of transistors. It is important to understand how self-heating may be for these new transistor structures as compared to FinFETs. The performance of advanced transistor structures (i.e., FinFET, Gate-All-Around FET, and Nanosheet FET) is simulated and compared under the constraints of the self-heating. An optimization guideline for nanosheet FETs is also proposed based on the study of various design parameters on the self-heating effects.},
}
EndNote citation:
%0 Thesis %A Ding, Fei %T Design for Performance and Reliability in Advanced CMOS Structures %I EECS Department, University of California, Berkeley %D 2020 %8 May 5 %@ UCB/EECS-2020-41 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-41.html %F Ding:EECS-2020-41