Lars Tatum

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2020-84

May 28, 2020

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-84.pdf

While advanced transistor structures have enabled gate length scaling below 20 nanometers and consequently enabled digital integrated circuits to increase in complexity with advancements in semiconductor manufacturing, they have not enabled similar improvement in analog IC performance due to degraded transconductance and increased gate leakage. Because of this, most analog ICs are manufactured using older-generation technology with long-channel transistors. The long channel length limits the transistor maximum oscillation frequency, however. In this study, technology computer-aided design simulations are used to assess the potential benefits of a quasi-planar segmented-channel transistor (SegFET) design for enhanced analog/RF performance, based on a mature 65 nm generation CMOS transistor technology.

Advisors: Tsu-Jae King Liu

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BibTeX citation:

@mastersthesis{Tatum:EECS-2020-84,
    Author= {Tatum, Lars},
    Editor= {King Liu, Tsu-Jae},
    Title= {Evaluation of Scaled Segmented Channel MOSFETs for Analog/RF Applications},
    School= {EECS Department, University of California, Berkeley},
    Year= {2020},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-84.html},
    Number= {UCB/EECS-2020-84},
    Abstract= {While advanced transistor structures have enabled gate length scaling below 20 nanometers and consequently enabled digital integrated circuits to increase in complexity with advancements in semiconductor manufacturing, they have not enabled similar improvement in analog IC performance due to degraded transconductance and increased gate leakage. Because of this, most analog ICs are manufactured using older-generation technology with long-channel transistors. The long channel length limits the transistor maximum oscillation frequency, however. In this study, technology computer-aided design simulations are used to assess the potential benefits of a quasi-planar segmented-channel transistor (SegFET) design for enhanced analog/RF performance, based on a mature 65 nm generation CMOS transistor technology.},
}

EndNote citation:

%0 Thesis
%A Tatum, Lars 
%E King Liu, Tsu-Jae 
%T Evaluation of Scaled Segmented Channel MOSFETs for Analog/RF Applications
%I EECS Department, University of California, Berkeley
%D 2020
%8 May 28
%@ UCB/EECS-2020-84
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-84.html
%F Tatum:EECS-2020-84