Design and Application of a Co-Simulation Framework for Chisel

Ryan Lund

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2021-133
May 15, 2021

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-133.pdf

As the cost to design chips increases, an ever-growing portion of the design cycle is spent in pre-silicon verification. When performed in industry, this verification work is backed by closed-source tools that require licenses for use. However, in the open-source domain, developers often lack access to similar verification resources.

This work aims to increase access to verification tools in the open-source space through the introduction of an instruction-accurate co-simulation framework for Chisel (CFC). The framework is designed to accelerate the verification of tightly coupled accelerators by pairing a functional model of a Rocket Chip-based core with an RTL simulation of an accelerator under test.

CFC implements a series of tools and utilities to elaborate and simulate RoCC accelerators removed from full-SoC context. Additionally, it contains utilities to convert hardware bundles to and from protocol buffers. These elements are used along with verification IP from the Chisel Verification Repository to create tools that connect a modified version of the Spike ISA simulator to an RTL simulation of a RoCC accelerator. When this connection is orchestrated by CFC's manager object, the two simulations form a coherent model of a full SoC. This allows SoC-level workloads to be run at RTL fidelity on an accelerator without the overhead associated with simulating the rest of the SoC at RTL accuracy.

Beyond detailing the design of CFC, this thesis demonstrates its impact by testing CFC on Gemmini, an open-source matrix multiplication network accelerator generator. With the additional optimization of ChiselTest binary caching, these tests show the potential for up to 9.72x speedup in test run time when compared to a full-SoC RTL simulation.

Advisor: Borivoje Nikolic


BibTeX citation:

@mastersthesis{Lund:EECS-2021-133,
    Author = {Lund, Ryan},
    Title = {Design and Application of a Co-Simulation Framework for Chisel},
    School = {EECS Department, University of California, Berkeley},
    Year = {2021},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-133.html},
    Number = {UCB/EECS-2021-133},
    Abstract = {As the cost to design chips increases, an ever-growing portion of the design cycle is spent in pre-silicon verification. When performed in industry, this verification work is backed by closed-source tools that require licenses for use. However, in the open-source domain, developers often lack access to similar verification resources. 

This work aims to increase access to verification tools in the open-source space through the introduction of an instruction-accurate co-simulation framework for Chisel (CFC). The framework is designed to accelerate the verification of tightly coupled accelerators by pairing a functional model of a Rocket Chip-based core with an RTL simulation of an accelerator under test. 

CFC implements a series of tools and utilities to elaborate and simulate RoCC accelerators removed from full-SoC context. Additionally, it contains utilities to convert hardware bundles to and from protocol buffers. These elements are used along with verification IP from the Chisel Verification Repository to create tools that connect a modified version of the Spike ISA simulator to an RTL simulation of a RoCC accelerator. When this connection is orchestrated by CFC's manager object, the two simulations form a coherent model of a full SoC. This allows SoC-level workloads to be run at RTL fidelity on an accelerator without the overhead associated with simulating the rest of the SoC at RTL accuracy.

Beyond detailing the design of CFC, this thesis demonstrates its impact by testing CFC on Gemmini, an open-source matrix multiplication network accelerator generator. With the additional optimization of ChiselTest binary caching, these tests show the potential for up to 9.72x speedup in test run time when compared to a full-SoC RTL simulation.}
}

EndNote citation:

%0 Thesis
%A Lund, Ryan
%T Design and Application of a Co-Simulation Framework for Chisel
%I EECS Department, University of California, Berkeley
%D 2021
%8 May 15
%@ UCB/EECS-2021-133
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2021/EECS-2021-133.html
%F Lund:EECS-2021-133