Steven Lu

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2022-94

May 13, 2022

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-94.pdf

Many NP-hard combinatorial optimization problems have practical applications in modern society, from vehicle routing to ASIC place-and-route for digital flows. However, traditional synchronous processor-based solutions struggle to keep up with the demands imposed by these problems, scaling exponentially with the input problem size. The Salahuddin group recently taped out the PASSOv1 processor, an asynchronous stochastic processor that demonstrates a significant power and performance improvement in solving a 100-node max-cut problem over other state-of-the-art systems. This report provides an analysis of the power, performance, and area of the processor’s analog core to facilitate the redesign process for future iterations of the chip. In addition, the report explores a potential lower-power topology to be used as a replacement for one of the chip’s subcircuits to reduce the power consumption.

Advisors: Sayeef Salahuddin

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BibTeX citation:

@mastersthesis{Lu:EECS-2022-94,
    Author= {Lu, Steven},
    Title= {Power, Performance, and Area Analysis of Asynchronous Stochastic Neural Accelerator PASSOv1},
    School= {EECS Department, University of California, Berkeley},
    Year= {2022},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-94.html},
    Number= {UCB/EECS-2022-94},
    Abstract= {Many NP-hard combinatorial optimization problems have practical applications in modern society, from vehicle routing to ASIC place-and-route for digital flows. However, traditional synchronous processor-based solutions struggle to keep up with the demands imposed by these problems, scaling exponentially with the input problem size. The Salahuddin group recently taped out the PASSOv1 processor, an asynchronous stochastic processor that demonstrates a significant power and performance improvement in solving a 100-node max-cut problem over other state-of-the-art systems. This report provides an analysis of the power, performance, and area of the processor’s analog core to facilitate the redesign process for future iterations of the chip. In addition, the report explores a potential lower-power topology to be used as a replacement for one of the chip’s subcircuits to reduce the power consumption.},
}

EndNote citation:

%0 Thesis
%A Lu, Steven 
%T Power, Performance, and Area Analysis of Asynchronous Stochastic Neural Accelerator PASSOv1
%I EECS Department, University of California, Berkeley
%D 2022
%8 May 13
%@ UCB/EECS-2022-94
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS-2022-94.html
%F Lu:EECS-2022-94