Reza Sajadiany

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2023-142

May 12, 2023

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-142.pdf

As the software requirements for hardware implementations become more complex, the need for agile development of a full system becomes more apparent. The design of complex hardware systems requires engineering efforts at different levels of abstraction layers. This design process becomes more efficient when the units that make up a system are separated by defined interfaces and communicate over a fixed protocol. A full system in the context of a system-on-chip must adhere to protocols defined at the architectural level. Once such protocol is defined for memory devices. Today’s workloads are often data-driven and need to access larger working sets of memory; however, the on-die memory system is limited by area and the power envelope of the target design. An off-chip volatile memory provides high-density memory implemented in less complex transistor nodes and provides the benefit of a large backing memory for the whole system. In addition, the most significant delays in modern systems are due to cache misses and cache refills from the DRAM. A typical delay estimate for such events is believed to be on the order of hundreds of cycles of the CPU clock. A memory controller is a crucial unit in the system that contributes to cache refill delays and the efficiency and bandwidth of the memory hierarchy. LPDDR4X represents a generation of memory devices defined by the JEDEC organization that implement the defined set of functionalities specified by the JEDEC standard for memory devices. This common standard unifies the protocol the memory controller designer needs to implement for a compatible DRAM device to function properly. In this thesis, I will describe my contribution to the implementation of a compatible memory controller design. This thesis focuses on an overview of the LPDDR4X and DRAM, design specifications and requirements, the architecture, and the micro-architecture of our LPDDR4X implementation. This implementation is included in UC Berkeley’s Chipyard SoC generator and has been done in the Chisel hardware description language.

Advisors: Borivoje Nikolic

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BibTeX citation:

@mastersthesis{Sajadiany:EECS-2023-142,
    Author= {Sajadiany, Reza},
    Title= {Implementation of an Open-Source Generator for LPDDR4X Memory Controller},
    School= {EECS Department, University of California, Berkeley},
    Year= {2023},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-142.html},
    Number= {UCB/EECS-2023-142},
    Abstract= {As the software requirements for hardware implementations become more complex, the need for agile development of a full system becomes more apparent. The design of complex hardware systems requires engineering efforts at different levels of abstraction layers. This design process becomes more efficient when the units that make up a system are separated by defined interfaces and communicate over a fixed protocol. A full system in the context of a system-on-chip must adhere to protocols defined at the architectural level. Once such protocol is defined for memory devices. Today’s workloads are often data-driven and need to access larger working sets of memory; however, the on-die memory system is limited by area and the power envelope of the target design. An off-chip volatile memory provides high-density memory implemented in less complex transistor nodes and provides the benefit of a large backing memory for the whole system.
In addition, the most significant delays in modern systems are due to cache misses and cache refills from the DRAM. A typical delay estimate for such events is believed to be on the order of hundreds of cycles of the CPU clock. A memory controller is a crucial unit in the system that contributes to cache refill delays and the efficiency and bandwidth of the memory hierarchy.
LPDDR4X represents a generation of memory devices defined by the JEDEC organization that implement the defined set of functionalities specified by the JEDEC standard for memory devices. This common standard unifies the protocol the memory controller designer needs to implement for a compatible DRAM device to function properly. In this thesis, I will describe my contribution to the implementation of a compatible memory controller design. This thesis focuses on an overview of the LPDDR4X and DRAM, design specifications and requirements, the architecture, and the micro-architecture of our LPDDR4X implementation. This implementation is included in UC Berkeley’s Chipyard SoC generator and has been done in the Chisel hardware description language.},
}

EndNote citation:

%0 Thesis
%A Sajadiany, Reza 
%T Implementation of an Open-Source Generator for LPDDR4X Memory Controller
%I EECS Department, University of California, Berkeley
%D 2023
%8 May 12
%@ UCB/EECS-2023-142
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-142.html
%F Sajadiany:EECS-2023-142