Animesh Agrawal

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2023-168

May 12, 2023

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-168.pdf

Motivated by the breakdown of Dennard scaling and current slowdown in CMOS scaling, SoC designers have increasingly embraced heterogeneity to meet power, performance, and area constraints. As SoC designs increase in scale, networks-on-chip (NoCs), have grown in prominence and complexity, becoming responsible for a significant fraction of an SoC's power consumption. However, NoCs are highly parameterizable and support a diverse set of constructions, making it crucial for designers to have access to feedback about a NoC design's power consumption early in the design phase.

In this thesis, we present an ML-based, workload aware, architectural power model for networks on chip (NoCs). We identify NoC architectural parameters most relevant to power consumption and construct a framework to generate a diverse training dataset of NoC configurations covering a range of power responses. We use the identified parameters and generated dataset to train a machine learning model capable of estimating NoC router power consumption and evaluate our model on realistic NoC designs routing simulated network traffic. Finally, we also present our progress towards constructing a NoC power model for NoC routers with heterogeneous channel configurations.

Advisors: Borivoje Nikolic

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BibTeX citation:

@mastersthesis{Agrawal:EECS-2023-168,
    Author= {Agrawal, Animesh},
    Title= {An Architectural Power Model for Networks on Chip},
    School= {EECS Department, University of California, Berkeley},
    Year= {2023},
    Month= {May},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-168.html},
    Number= {UCB/EECS-2023-168},
    Abstract= {Motivated by the breakdown of Dennard scaling and current slowdown in CMOS scaling, SoC designers have increasingly embraced heterogeneity to meet power, performance, and area constraints. As SoC designs increase in scale, networks-on-chip (NoCs), have grown in prominence and complexity, becoming responsible for a significant fraction of an SoC's power consumption. However, NoCs are highly parameterizable and support a diverse set of constructions, making it crucial for designers to have access to feedback about a NoC design's power consumption early in the design phase. 

In this thesis, we present an ML-based, workload aware, architectural power model for networks on chip (NoCs). We identify NoC architectural parameters most relevant to power consumption and construct a framework to generate a diverse training dataset of NoC configurations covering a range of power responses. We use the identified parameters and generated dataset to train a machine learning model capable of estimating NoC router power consumption and evaluate our model on realistic NoC designs routing simulated network traffic. Finally, we also present our progress towards constructing a NoC power model for NoC routers with heterogeneous channel configurations.},
}

EndNote citation:

%0 Thesis
%A Agrawal, Animesh 
%T An Architectural Power Model for Networks on Chip
%I EECS Department, University of California, Berkeley
%D 2023
%8 May 12
%@ UCB/EECS-2023-168
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-168.html
%F Agrawal:EECS-2023-168