Ayan Biswas

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2023-213

August 11, 2023

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-213.pdf

With the ever increasing bandwidth demand in high performance computing, network and communications, machine learning applications, etc, wireline data transfer between multiple chips on the same package has been doubling in per-lane data rate every 3-4 years. The challenging design complexity of the analog and mixed signal front-end circuits necessitates the use of automated process portable layout generators and closed loop design scripts to reduce the turn-around time from circuit design to tape-outs in advanced FinFET technology nodes.

To that end, this thesis introduces new feature improvements in the Berkeley Analog Generator (BAG) 3++, which is an open source framework for automating process portable circuit generation and encoding closed loop design methodologies. Then the thesis presents the design of a 160 Gbps NRZ transmitter (TX) targeting low loss (~3dB) ultra short reach channels for die-to-die data transfer, with 2 tap FFE for pre-equalization. Some major challenges in this effort are the design of a high speed 8:1 mux stage using inductor-based peaking topologies, and a novel method of creating the 1 UI delayed data stream for the FFE precursor using the available octature clock phases. The TX is taped out in Intel16 process as a part of a complete 160 Gbps NRZ transceiver design, and tested in loopback mode by serially transmitting data to the receiver over a 8.5 mm differential channel on package.

Advisors: Elad Alon and Vladimir Stojanovic

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BibTeX citation:

@phdthesis{Biswas:EECS-2023-213,
    Author= {Biswas, Ayan},
    Title= {Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters},
    School= {EECS Department, University of California, Berkeley},
    Year= {2023},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-213.html},
    Number= {UCB/EECS-2023-213},
    Abstract= {With the ever increasing bandwidth demand in high performance computing, network and communications, machine learning applications, etc, wireline data transfer between multiple chips on the same package has been doubling in per-lane data rate every 3-4 years. The challenging design complexity of the analog and mixed signal front-end circuits necessitates the use of automated process portable layout generators and closed loop design scripts to reduce the turn-around time from circuit design to tape-outs in advanced FinFET technology nodes. 

To that end, this thesis introduces new feature improvements in the Berkeley Analog Generator (BAG) 3++, which is an open source framework for automating process portable circuit generation and encoding closed loop design methodologies. Then the thesis presents the design of a 160 Gbps NRZ transmitter (TX) targeting low loss (~3dB) ultra short reach channels for die-to-die data transfer, with 2 tap FFE for pre-equalization. Some major challenges in this effort are the design of a high speed 8:1 mux stage using inductor-based peaking topologies, and a novel method of creating the 1 UI delayed data stream for the FFE precursor using the available octature clock phases. The TX is taped out in Intel16 process as a part of a complete 160 Gbps NRZ transceiver design, and tested in loopback mode by serially transmitting data to the receiver over a 8.5 mm differential channel on package.},
}

EndNote citation:

%0 Thesis
%A Biswas, Ayan 
%T Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters
%I EECS Department, University of California, Berkeley
%D 2023
%8 August 11
%@ UCB/EECS-2023-213
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-213.html
%F Biswas:EECS-2023-213