Tan Nguyen

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2023-284

December 15, 2023

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-284.pdf

With the increasing growth of complexity and heterogeneity of modern FPGA fabrics, the conventional digital design flow relying on the standard vendor tools, from synthesis to I'm plementation, has become more arduous than ever. This leads to an inordinate turn-around time which severely impacts the productivity of application developers in their quest to explore the design space. We propose an open-source tool flow built upon three principles: modularity, composability, and reusability to address the FPGA tooling productivity issue. Our tool flow features the design and implementation of Spatially Distributed Ensemble of Sockets (SPADES). SPADES modularizes an application into a parallel system of socket engines interconnected by a Network-on-chip. Each socket contains a fixed and reusable component for control and communication in addition to a custom partition tailored to specific application computation and memory demands. SPADES also presents a customized backend tool that allows flexible and rapid composition of the socket physical implementations to generate a complete design. The results demonstrate that SPADES is 7.1x faster on average by reducing hours of compile time to minutes, while achieving comparable system-level performance when compared to a standard vendor tool for a set of benchmarks targeting a state-of-the-art FPGA architecture.

Advisors: John Wawrzynek

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BibTeX citation:

@phdthesis{Nguyen:EECS-2023-284,
    Author= {Nguyen, Tan},
    Title= {A Modular Design Flow for NoC-embedded FPGAs},
    School= {EECS Department, University of California, Berkeley},
    Year= {2023},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-284.html},
    Number= {UCB/EECS-2023-284},
    Abstract= {With the increasing growth of complexity and heterogeneity of modern FPGA fabrics, the conventional digital design flow relying on the standard vendor tools, from synthesis to I'm plementation, has become more arduous than ever. This leads to an inordinate turn-around time which severely impacts the productivity of application developers in their quest to explore the design space. We propose an open-source tool flow built upon three principles: modularity, composability, and reusability to address the FPGA tooling productivity issue. Our tool flow features the design and implementation of Spatially Distributed Ensemble of Sockets (SPADES). SPADES modularizes an application into a parallel system of socket engines interconnected by a Network-on-chip. Each socket contains a fixed and reusable component for control and communication in addition to a custom partition tailored to specific application computation and memory demands. SPADES also presents a customized backend tool that allows flexible and rapid composition of the socket physical implementations to generate a complete design. The results demonstrate that SPADES is 7.1x faster on average by reducing hours of compile time to minutes, while achieving comparable system-level performance when compared to a standard vendor tool for a set of benchmarks targeting a state-of-the-art FPGA architecture.},
}

EndNote citation:

%0 Thesis
%A Nguyen, Tan 
%T A Modular Design Flow for NoC-embedded FPGAs
%I EECS Department, University of California, Berkeley
%D 2023
%8 December 15
%@ UCB/EECS-2023-284
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2023/EECS-2023-284.html
%F Nguyen:EECS-2023-284