Krishnakumar Bhattaram and Pratik Brahma and Sayeef Salahuddin

EECS Department, University of California, Berkeley

Technical Report No. UCB/

May 1, 2024

http://www2.eecs.berkeley.edu/Pubs/TechRpts/Hold/bccf6cba8f7bfc992ae3385a4e4ed4ca.pdf

Modern microelectronic devices are composed of interfaces between a large number of materials, many of which are in amorphous or polycrystalline phases. Modeling such non- crystalline materials using first-principles methods such as density functional theory is often numerically intractable. Recently, graph neural networks (GNNs) have shown potential to achieve linear complexity with accuracies comparable to ab-initio methods. In this work, we demonstrate the applicability of GNNs to accelerate the atomistic computational pipeline for predicting macroscopic transistor transport characteristics via learning microscopic physical properties. We generate an amorphous HfO2-SiO2-Si semiconductor-dielectric transistor gate stack via GNN-predicted atomic forces, and show parity with experimental atomistic structure. We then identify limitations in the GNN architecture for prediction of electronic transport quantities including density of states and current density of states in silicon channels, and demonstrate high-fidelity reproduction of nonlocal confinement features through two novel, physically-motivated architectures. Finally, we explore the role of discrete symmetry equivariance on model performance on crystalline structures. This work paves the way for faster and more scalable methods to model modern advanced electronic devices, with applications in high-throughput and inverse design domains.

Advisors: Sayeef Salahuddin

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BibTeX citation:

@mastersthesis{Bhattaram:31372,
    Author= {Bhattaram, Krishnakumar and Brahma, Pratik and Salahuddin, Sayeef},
    Title= {Accelerated Modeling of Electronic Devices using Graph Neural Networks},
    School= {EECS Department, University of California, Berkeley},
    Year= {2024},
    Number= {UCB/},
    Abstract= {Modern microelectronic devices are composed of interfaces between a large number of materials, many of which are in amorphous or polycrystalline phases. Modeling such non- crystalline materials using first-principles methods such as density functional theory is often numerically intractable. Recently, graph neural networks (GNNs) have shown potential to achieve linear complexity with accuracies comparable to ab-initio methods. In this work, we demonstrate the applicability of GNNs to accelerate the atomistic computational pipeline for predicting macroscopic transistor transport characteristics via learning microscopic physical properties. We generate an amorphous HfO2-SiO2-Si semiconductor-dielectric transistor gate stack via GNN-predicted atomic forces, and show parity with experimental atomistic structure. We then identify limitations in the GNN architecture for prediction of electronic transport quantities including density of states and current density of states in silicon channels, and demonstrate high-fidelity reproduction of nonlocal confinement features through two novel, physically-motivated architectures. Finally, we explore the role of discrete symmetry equivariance on model performance on crystalline structures. This work paves the way for faster and more scalable methods to model modern advanced electronic devices, with applications in high-throughput and inverse design domains.},
}

EndNote citation:

%0 Thesis
%A Bhattaram, Krishnakumar 
%A Brahma, Pratik 
%A Salahuddin, Sayeef 
%T Accelerated Modeling of Electronic Devices using Graph Neural Networks
%I EECS Department, University of California, Berkeley
%D 2024
%8 May 1
%@ UCB/
%F Bhattaram:31372