Yicheng Zhu

EECS Department, University of California, Berkeley

Technical Report No. UCB/

May 1, 2024

http://www2.eecs.berkeley.edu/Pubs/TechRpts/Hold/b7716b5716094de1afe4fc16b5e71f10.pdf

Hybrid switched-capacitor (SC) converters have attracted increased attention due to their potential to provide improved solutions with higher efficiency and higher power density compared to conventional designs. As an emerging class of power converters, hybrid SC converters can leverage the greatly superior energy density of capacitors compared to inductors, while simultaneously benefiting from the improved figure-of-merit of low-voltage switching devices over their high-voltage counterparts. This dissertation explores the circuit topologies, control techniques, and analytical models for hybrid SC converters to enable higher performance.

First, this dissertation models and analyzes the effect of finite terminal capacitances on the performance of pure and resonant SC converters. By establishing a general output impedance model for each type of converter, the first part of this dissertation reveals that insufficient terminal capacitances can lead to a dramatic increase in output impedance and cause a considerable efficiency drop. Based on this analysis, a multi-resonant control technique is proposed to reduce terminal capacitances without sacrificing efficiency.

Second, this dissertation explores high-performance hybrid SC converters for direct 48 V to point-of-load (PoL) power conversion in data centers. High-performance processors (e.g., graphics processing units [GPUs], central processing units [CPUs], application-specific integrated circuits [ASICs], etc.) serve as the engine of data center computing platforms and the foundation for technical progress in areas such as artificial intelligence and autonomous vehicles. Due to the fast-growing demand for greater computational power, the electric power consumption of processors has increased dramatically in recent years and is approaching 1000 W, with core logic voltages below 1 V and peak current demand beyond 1000 A. At such high current levels, the large power distribution network (PDN) of the existing two-stage lateral power delivery architecture can lead to a dramatic voltage drop and unacceptable conduction losses, which significantly limits processor performance, reduces system energy efficiency, and hinders data center decarbonization and densification.

In pursuit of a more efficient and compact alternative to the existing solution, the second part of this dissertation introduces a family of high-performance 48-V-to-PoL hybrid SC voltage regulators, named the switching bus converter. Based on a single-stage vertical power delivery (VPD) architecture, the switching bus converter significantly reduces the PDN size and power conversion losses. Moreover, the proposed switching bus converter family strategically merges two or multiple conversion stages through switching buses, a type of intermediate bus with a switching voltage. Compared to the existing dc-bus-based architecture, the proposed switching-bus-based architecture does not require dc bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. In addition, this dissertation conducts a comparative performance analysis of different regulated hybrid SC topologies, which reveals that a larger SC conversion ratio is advantageous for achieving higher performance. Through the two-phase operation of the series-capacitor buck modules, the proposed switching bus converter extends the maximum duty ratio and enables a larger SC conversion ratio. Various circuit topologies from the switching bus converter family and their hardware prototypes are presented in this dissertation, including a 1500-A high-efficiency prototype and a high-density prototype with a practical form factor for VPD, which push the performance boundary for 48-V-to-PoL power conversion.

Advisors: Robert Pilawa-Podgurski

---

BibTeX citation:

@phdthesis{Zhu:31390,
    Author= {Zhu, Yicheng},
    Title= {High-Performance Hybrid Switched-Capacitor Power Converters: Circuit Topologies, Control Techniques, and Analytical Models},
    School= {EECS Department, University of California, Berkeley},
    Year= {2024},
    Number= {UCB/},
    Abstract= {Hybrid switched-capacitor (SC) converters have attracted increased attention due to their potential to provide improved solutions with higher efficiency and higher power density compared to conventional designs. As an emerging class of power converters, hybrid SC converters can leverage the greatly superior energy density of capacitors compared to inductors, while simultaneously benefiting from the improved figure-of-merit of low-voltage switching devices over their high-voltage counterparts. This dissertation explores the circuit topologies, control techniques, and analytical models for hybrid SC converters to enable higher performance.

First, this dissertation models and analyzes the effect of finite terminal capacitances on the performance of pure and resonant SC converters. By establishing a general output impedance model for each type of converter, the first part of this dissertation reveals that insufficient terminal capacitances can lead to a dramatic increase in output impedance and cause a considerable efficiency drop. Based on this analysis, a multi-resonant control technique is proposed to reduce terminal capacitances without sacrificing efficiency.

Second, this dissertation explores high-performance hybrid SC converters for direct 48 V to point-of-load (PoL) power conversion in data centers. High-performance processors (e.g., graphics processing units [GPUs], central processing units [CPUs], application-specific integrated circuits [ASICs], etc.) serve as the engine of data center computing platforms and the foundation for technical progress in areas such as artificial intelligence and autonomous vehicles. Due to the fast-growing demand for greater computational power, the electric power consumption of processors has increased dramatically in recent years and is approaching 1000 W, with core logic voltages below 1 V and peak current demand beyond 1000 A. At such high current levels, the large power distribution network (PDN) of the existing two-stage lateral power delivery architecture can lead to a dramatic voltage drop and unacceptable conduction losses, which significantly limits processor performance, reduces system energy efficiency, and hinders data center decarbonization and densification.

In pursuit of a more efficient and compact alternative to the existing solution, the second part of this dissertation introduces a family of high-performance 48-V-to-PoL hybrid SC voltage regulators, named the switching bus converter. Based on a single-stage vertical power delivery (VPD) architecture, the switching bus converter significantly reduces the PDN size and power conversion losses. Moreover, the proposed switching bus converter family strategically merges two or multiple conversion stages through switching buses, a type of intermediate bus with a switching voltage. Compared to the existing dc-bus-based architecture, the proposed switching-bus-based architecture does not require dc bus capacitors, reduces the number of switches, and ensures complete soft-charging operation. In addition, this dissertation conducts a comparative performance analysis of different regulated hybrid SC topologies, which reveals that a larger SC conversion ratio is advantageous for achieving higher performance. Through the two-phase operation of the series-capacitor buck modules, the proposed switching bus converter extends the maximum duty ratio and enables a larger SC conversion ratio. Various circuit topologies from the switching bus converter family and their hardware prototypes are presented in this dissertation, including a 1500-A high-efficiency prototype and a high-density prototype with a practical form factor for VPD, which push the performance boundary for 48-V-to-PoL power conversion.},
}

EndNote citation:

%0 Thesis
%A Zhu, Yicheng 
%T High-Performance Hybrid Switched-Capacitor Power Converters: Circuit Topologies, Control Techniques, and Analytical Models
%I EECS Department, University of California, Berkeley
%D 2024
%8 May 1
%@ UCB/
%F Zhu:31390