Lars Tatum

EECS Department, University of California, Berkeley

Technical Report No. UCB/

May 1, 2024

http://www2.eecs.berkeley.edu/Pubs/TechRpts/Hold/009dc841954eafa5d8c77b6fedff4106.pdf

The rapid technological advancement over the past century, is a manifestation of Kurzweil's Law of Accelerating Returns. This theory, proposed by Ray Kurzweil, posits that technological progress accelerates exponentially, with each innovation spurring further advancements. This exponential growth has profound implications across various domains, driving innovation and fueling economic growth. A notable outcome of this progress is Generative AI, which is transforming communication, work, and learning, further accelerating technological advancement. Since the 1970s, solid-state integrated circuit (IC) technology has been crucial to this exponential growth. Moore's Law, which observes the doubling of transistors on a chip approximately every two years, has enabled continuous enhancements in computational power and cost efficiency. However, around 2005, Dennard Scaling, a method for improving IC performance by scaling down MOSFETs, became impractical due to physical constraints. The future of IC technology faces significant challenges in maintaining improvements in Performance, Power, Area, and Cost (PPAC). Advancements in each of these aspects are increasingly interdependent, with improvements in one area often resulting in trade-offs in another. For instance, enhancing standby power consumption is constrained by the Boltzmann limit of the subthreshold slope, while performance is limited by parasitic resistances and capacitances. The semiconductor industry's continuous improvement is vital to sustaining technological progress, as predicted by Kurzweil's Law. Maintaining this trajectory is crucial to avoiding stagnation in technological capabilities. The dissertation aims to explore novel approaches to advancing CMOS technology platforms without significant trade-offs in PPAC, leveraging "Device and Circuit Cleverness" as noted by Gordon Moore. A vertically oriented, nonvolatile Back End of Line Nanoelectromechanical Switch (NV BEOL NEMS) is introduced as an emerging nonvolatile memory device using compact-finite-element-method simulations. BEOL NEMS can be integrated with CMOS processes, requiring only air-gap technology. A new differential half-select scheme enables dense NEMS arrays with low transistor overhead. A CMOS-compatible, high PVCR negative differential resistance (NDR) device based on an optimized ferroelectric field-effect-transistor (FeFET) is proposed. TCAD studies explain its operation and optimization techniques to achieve peak currents over 400 µA/µm and PVCR over 10^6. Finally, SRAM bit-cells based on the NDR FeFET are discussed and benchmarked against 6T CMOS FinFET SRAM using mixed-mode TCAD simulations. NDR FeFET SRAM offers significantly lower standby power, requires fewer devices, and leverages its unique hysteresis to reduce VDD, achieve low retention Vmin, and enable nonvolatile operation.

Advisors: Tsu-Jae King Liu

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BibTeX citation:

@phdthesis{Tatum:31436,
    Author= {Tatum, Lars},
    Editor= {King Liu, Tsu-Jae},
    Title= {Compact Device Technologies for Compact Integrated Systems},
    School= {EECS Department, University of California, Berkeley},
    Year= {2024},
    Number= {UCB/},
    Abstract= {The rapid technological advancement over the past century, is a manifestation of Kurzweil's Law of Accelerating Returns. This theory, proposed by Ray Kurzweil, posits that technological progress accelerates exponentially, with each innovation spurring further advancements. This exponential growth has profound implications across various domains, driving innovation and fueling economic growth. A notable outcome of this progress is Generative AI, which is transforming communication, work, and learning, further accelerating technological advancement.
Since the 1970s, solid-state integrated circuit (IC) technology has been crucial to this exponential growth. Moore's Law, which observes the doubling of transistors on a chip approximately every two years, has enabled continuous enhancements in computational power and cost efficiency. However, around 2005, Dennard Scaling, a method for improving IC performance by scaling down MOSFETs, became impractical due to physical constraints. The future of IC technology faces significant challenges in maintaining improvements in Performance, Power, Area, and Cost (PPAC). Advancements in each of these aspects are increasingly interdependent, with improvements in one area often resulting in trade-offs in another. For instance, enhancing standby power consumption is constrained by the Boltzmann limit of the subthreshold slope, while performance is limited by parasitic resistances and capacitances. The semiconductor industry's continuous improvement is vital to sustaining technological progress, as predicted by Kurzweil's Law. Maintaining this trajectory is crucial to avoiding stagnation in technological capabilities. The dissertation aims to explore novel approaches to advancing CMOS technology platforms without significant trade-offs in PPAC, leveraging "Device and Circuit Cleverness" as noted by Gordon Moore. 
A vertically oriented, nonvolatile Back End of Line Nanoelectromechanical Switch (NV BEOL NEMS) is introduced as an emerging nonvolatile memory device using compact-finite-element-method simulations. BEOL NEMS can be integrated with CMOS processes, requiring only air-gap technology. A new differential half-select scheme enables dense NEMS arrays with low transistor overhead.
A CMOS-compatible, high PVCR negative differential resistance (NDR) device based on an optimized ferroelectric field-effect-transistor (FeFET) is proposed. TCAD studies explain its operation and optimization techniques to achieve peak currents over 400 µA/µm and PVCR over 10^6.
Finally, SRAM bit-cells based on the NDR FeFET are discussed and benchmarked against 6T CMOS FinFET SRAM using mixed-mode TCAD simulations. NDR FeFET SRAM offers significantly lower standby power, requires fewer devices, and leverages its unique hysteresis to reduce VDD, achieve low retention Vmin, and enable nonvolatile operation.},
}

EndNote citation:

%0 Thesis
%A Tatum, Lars 
%E King Liu, Tsu-Jae 
%T Compact Device Technologies for Compact Integrated Systems
%I EECS Department, University of California, Berkeley
%D 2024
%8 May 1
%@ UCB/
%F Tatum:31436