SonicSim: Socket-based Hardware Co-Simulation With Inter-process Communication
Richard Yan
EECS Department, University of California, Berkeley
Technical Report No. UCB/EECS-2024-61
May 7, 2024
http://www2.eecs.berkeley.edu/Pubs/TechRpts/2024/EECS-2024-61.pdf
Modern computer architecture is increasingly large and heterogeneous, and coherent co-simulation of the design is an effective tool to quickly iterate the design of individual sub-components and lower the cost of design and evaluation. However, scalably applying co-simulation methods to a variety of hardware designs is challenging, especially because different hardware blocks often necessitate the use of their own tools and simulation frameworks, requiring a lot of manual work to integrate them into a single coherent simulation.
To address these shortcomings, we propose SonicSim, a novel co-simulation framework with a specific focus on scalability and low effort of integration. SonicSim defines a simple inter-process communication protocol across hardware blocks, and supports point-to-point connections and central server-client architecture to better scale to more simulation endpoints. When leveraging a lightweight MMIO-based host-target interface, our framework lifts the integration to the software workload level, requiring minimal modifications in the target hardware design. From the case studies of CPU-GPU co-simulation and many-accelerator co-simulation, we demonstrate that SonicSim enables mix-and-matching of different simulation backends across the design components and achieves significant simulation speedup with accurate cycle time prediction, exposing useful tradeoffs between simulation speed and fidelity to the designer. Finally, we quantify that applying our framework requires minimal lines-of-code changes to the target hardware and software workload.
Advisors: Sophia Shao
BibTeX citation:
@mastersthesis{Yan:EECS-2024-61, Author= {Yan, Richard}, Title= {SonicSim: Socket-based Hardware Co-Simulation With Inter-process Communication}, School= {EECS Department, University of California, Berkeley}, Year= {2024}, Month= {May}, Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2024/EECS-2024-61.html}, Number= {UCB/EECS-2024-61}, Abstract= {Modern computer architecture is increasingly large and heterogeneous, and coherent co-simulation of the design is an effective tool to quickly iterate the design of individual sub-components and lower the cost of design and evaluation. However, scalably applying co-simulation methods to a variety of hardware designs is challenging, especially because different hardware blocks often necessitate the use of their own tools and simulation frameworks, requiring a lot of manual work to integrate them into a single coherent simulation. To address these shortcomings, we propose SonicSim, a novel co-simulation framework with a specific focus on scalability and low effort of integration. SonicSim defines a simple inter-process communication protocol across hardware blocks, and supports point-to-point connections and central server-client architecture to better scale to more simulation endpoints. When leveraging a lightweight MMIO-based host-target interface, our framework lifts the integration to the software workload level, requiring minimal modifications in the target hardware design. From the case studies of CPU-GPU co-simulation and many-accelerator co-simulation, we demonstrate that SonicSim enables mix-and-matching of different simulation backends across the design components and achieves significant simulation speedup with accurate cycle time prediction, exposing useful tradeoffs between simulation speed and fidelity to the designer. Finally, we quantify that applying our framework requires minimal lines-of-code changes to the target hardware and software workload.}, }
EndNote citation:
%0 Thesis %A Yan, Richard %T SonicSim: Socket-based Hardware Co-Simulation With Inter-process Communication %I EECS Department, University of California, Berkeley %D 2024 %8 May 7 %@ UCB/EECS-2024-61 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2024/EECS-2024-61.html %F Yan:EECS-2024-61