Aviral Pandey

EECS Department, University of California, Berkeley

Technical Report No. UCB/

December 1, 2025

Neural recording implants are an integral part of Brain Computer Interfaces (BCIs) used in both neuroscience research, clinical applications, and emerging wearable applications. In the first half of this thesis, I outline a neural recording application specific integrated circuit (ASIC) optimized for recording signals from an ear-worn EEG recording device we call Ear-EEG. A key issue with wearable devices is motion artifacts, or interferers that arise from users moving while wearing the device. To measure these motion artifacts, the devices presented here simultaneously measure EEG and Electrode-Skin Interface Impedance (ESI), enabling downstream cancellation through signal processing.

The remainder of this thesis will discuss techniques to reduce power in implantable neural recording devices. The power consumption of high channel count implants is generally dominated by the analog circuits, particularly the low-noise amplifier and data converter used to amplify and digitize neural signals. While circuit design techniques exist to reduce the power of these components, we demonstrate a system level approach that leverages the learning- based decoding of neural recordings to save overall system power. Our simulations show that an array of resolution reconfigurable front-ends can save up to an order of magnitude in power for a small reduction in decoding accuracy. This power savings is demonstrated across three different decoding datasets, seizure detection, EMG gesture recognition, and non-human primate motor decoding. Furthermore, the approach is agnostic to the learning algorithm and results are demonstrated with logistic regression, support vector machine, random forest and neural network classifiers. I also compare to existing techniques to reduce system power using sparse channel selection, and show that resolution reconfiguration can consume up to 5× less power for equivalent accuracy. Finally, I show a circuit implemen- tation of a resolution reconfigurable neural recording front-end, and present measurement results.

Advisors: Rikky Muller

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BibTeX citation:

@phdthesis{Pandey:31776,
    Author= {Pandey, Aviral},
    Title= {Application Specific and Resolution Reconfigurable Neural Recording Devices},
    School= {EECS Department, University of California, Berkeley},
    Year= {2025},
    Number= {UCB/},
    Abstract= {Neural recording implants are an integral part of Brain Computer Interfaces (BCIs) used in both neuroscience research, clinical applications, and emerging wearable applications. In the first half of this thesis, I outline a neural recording application specific integrated circuit (ASIC) optimized for recording signals from an ear-worn EEG recording device we call Ear-EEG. A key issue with wearable devices is motion artifacts, or interferers that arise
from users moving while wearing the device. To measure these motion artifacts, the devices presented here simultaneously measure EEG and Electrode-Skin Interface Impedance (ESI), enabling downstream cancellation through signal processing. 

The remainder of this thesis will discuss techniques to reduce power in implantable neural recording devices. The power consumption of high channel count implants is generally dominated by the analog circuits, particularly the low-noise amplifier and data converter used to amplify and digitize neural signals. While circuit design techniques exist to reduce the power of these components, we demonstrate a system level approach that leverages the learning-
based decoding of neural recordings to save overall system power. Our simulations show that an array of resolution reconfigurable front-ends can save up to an order of magnitude in power for a small reduction in decoding accuracy. This power savings is demonstrated
across three different decoding datasets, seizure detection, EMG gesture recognition, and non-human primate motor decoding. Furthermore, the approach is agnostic to the learning
algorithm and results are demonstrated with logistic regression, support vector machine, random forest and neural network classifiers. I also compare to existing techniques to reduce
system power using sparse channel selection, and show that resolution reconfiguration can consume up to 5× less power for equivalent accuracy. Finally, I show a circuit implemen-
tation of a resolution reconfigurable neural recording front-end, and present measurement results.},
}

EndNote citation:

%0 Thesis
%A Pandey, Aviral 
%T Application Specific and Resolution Reconfigurable Neural Recording Devices
%I EECS Department, University of California, Berkeley
%D 2025
%8 December 1
%@ UCB/
%F Pandey:31776