Kunmo Kim

EECS Department, University of California, Berkeley

Technical Report No. UCB/

May 1, 2025

This thesis investigates nonlinear feed-forward equalization and scalable ADC-based receiver architectures for high-speed serial links, with the goal of relaxing timing bottlenecks and improving the scalability of next-generation SerDes.

The first part of this work introduces a low-complexity, low-latency nonlinear feed-forward equalizer that cancels both the first precursor and first postcursor ISI without relying on a feedback loop. The proposed equalizer is constructed by combining two symmetric nonlinear feed-forward structures together with pattern detection and filtering, avoiding noise amplification and UI-critical feedback timing. Simulation results show that its equalization capability exceeds that of a conventional sub-optimal FFE+DFE combination under comparable complexity and latency.

The second part of the thesis focuses on cascaded sliding-block DFE (SB-DFE). A more rigorous error-propagation framework is developed for conventional DFE, clarifying how the error propagation effect of DFE can be accurately analyzed in the presence of residual ISI, how it impacts BER, and how the expected burst-error length can be derived and related to the BER. In addition, cascaded SB-DFE architecture is proposed to mitigate the ISI-dependent latency and timing constraints of conventional SB-DFE, while preserving most of its performance advantages. This provides a path toward deeper nonlinear equalization in highly dispersive channels without timing constraints.

The final part of the thesis addresses the scalability of ADC-based SerDes receivers. A 128-GS/s ADC architecture is presented that achieves the target sampling rate using only 16-way time interleaving, significantly reducing the number of sub-ADCs compared to many recent designs. Circuit and architectural techniques are used to improve sampling efficiency and relax clock distribution and calibration overhead, illustrating a more scalable path for future high-speed ADC-based links.

Advisors: Ali Niknejad

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BibTeX citation:

@phdthesis{Kim:32004,
    Author= {Kim, Kunmo},
    Title= {Nonlinear Feed-Forward Equalization and ADC-based Receiver Architecture for High-Speed Serial Links},
    School= {EECS Department, University of California, Berkeley},
    Year= {2025},
    Month= {Dec},
    Number= {UCB/},
    Abstract= {This thesis investigates nonlinear feed-forward equalization and scalable ADC-based receiver architectures for high-speed serial links, with the goal of relaxing timing bottlenecks and improving the scalability of next-generation SerDes. 

The first part of this work introduces a low-complexity, low-latency nonlinear feed-forward equalizer that cancels both the first precursor and first postcursor ISI without relying on a feedback loop. The proposed equalizer is constructed by combining two symmetric nonlinear feed-forward structures together with pattern detection and filtering, avoiding noise amplification and UI-critical feedback timing. Simulation results show that its equalization capability exceeds that of a conventional sub-optimal FFE+DFE combination under comparable complexity and latency.

The second part of the thesis focuses on cascaded sliding-block DFE (SB-DFE). A more rigorous error-propagation framework is developed for conventional DFE, clarifying how the error propagation effect of DFE can be accurately analyzed in the presence of residual ISI, how it impacts BER, and how the expected burst-error length can be derived and related to the BER. In addition, cascaded SB-DFE architecture is proposed to mitigate the ISI-dependent latency and timing constraints of conventional SB-DFE, while preserving most of its performance advantages. This provides a path toward deeper nonlinear equalization in highly dispersive channels without timing constraints.

The final part of the thesis addresses the scalability of ADC-based SerDes receivers. A 128-GS/s ADC architecture is presented that achieves the target sampling rate using only 16-way time interleaving, significantly reducing the number of sub-ADCs compared to many recent designs. Circuit and architectural techniques are used to improve sampling efficiency and relax clock distribution and calibration overhead, illustrating a more scalable path for future high-speed ADC-based links.},
}

EndNote citation:

%0 Thesis
%A Kim, Kunmo 
%T Nonlinear Feed-Forward Equalization and ADC-based Receiver Architecture for High-Speed Serial Links
%I EECS Department, University of California, Berkeley
%D 2025
%8 May 1
%@ UCB/
%F Kim:32004