LLM-Powered EDA Log Analysis for Effective Design Debugging

Rohit Kanagal

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2025-48
May 12, 2025

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-48.pdf

In modern chip design, synthesis and place-and-route tools generate extensive log files containing critical insights into possible issues with the design. However, these logs are often long, unstructured, and difficult to interpret, especially for novice designers. This thesis explores the use of Large Language Models (LLMs), particularly GPT-4o, to automate Electronic Design Automation (EDA) log analysis (particularly synthesis) and support early-stage debugging.

We present a structured pipeline that leverages LLMs for table extraction, synthesis issue detection, and HDL/constraint suggestions. A one-shot learning approach for table extraction yielded high accuracy in identifying tables with prior descriptions, outperforming traditional rule-based methods. For issue identification, a hybrid system combining rule-based log filtering with GPT-4o achieved 100% detection accuracy and 89% correct fix rate—dramatically outperforming a Retrieval-Augmented Generation (RAG) baseline, which achieved only 56% detection and 11% fix rates.

Building upon this, we introduce a multi-agent debugging system with modular components for synthesis evaluation, log structuring, issue analysis, and HDL rewriting. Across six Verilog designs—including ALU, FIFO, GCD, and a 3-stage RISC-V CPU—the multi-agent system resolved 93.7% of synthesis issues on average, compared to 57% by GPT-4o in single-pass mode.

Finally, we introduce AutoTA, a lightweight LLM-powered teaching assistant for digital systems courses like UC Berkeley's EECS 151, which provides actionable, synthesis-aware feedback without code edits. AutoTA improves student understanding of synthesis issues and optimizes the feedback loop between instructors and students.

Advisor: Borivoje Nikolic

"; ?>

BibTeX citation:

@mastersthesis{Kanagal:EECS-2025-48,
    Author = {Kanagal, Rohit},
    Title = {LLM-Powered EDA Log Analysis for Effective Design Debugging},
    School = {EECS Department, University of California, Berkeley},
    Year = {2025},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-48.html},
    Number = {UCB/EECS-2025-48},
    Abstract = {In modern chip design, synthesis and place-and-route tools generate extensive log files containing critical insights into possible issues with the design. However, these logs are often long, unstructured, and difficult to interpret, especially for novice designers. This thesis explores the use of Large Language Models (LLMs), particularly GPT-4o, to automate Electronic Design Automation (EDA) log analysis (particularly synthesis) and support early-stage debugging.

We present a structured pipeline that leverages LLMs for table extraction, synthesis issue detection, and HDL/constraint suggestions. A one-shot learning approach for table extraction yielded high accuracy in identifying tables with prior descriptions, outperforming traditional rule-based methods. For issue identification, a hybrid system combining rule-based log filtering with GPT-4o achieved 100% detection accuracy and 89% correct fix rate—dramatically outperforming a Retrieval-Augmented Generation (RAG) baseline, which achieved only 56% detection and 11% fix rates.

Building upon this, we introduce a multi-agent debugging system with modular components for synthesis evaluation, log structuring, issue analysis, and HDL rewriting. Across six Verilog designs—including ALU, FIFO, GCD, and a 3-stage RISC-V CPU—the multi-agent system resolved 93.7% of synthesis issues on average, compared to 57% by GPT-4o in single-pass mode.

Finally, we introduce AutoTA, a lightweight LLM-powered teaching assistant for digital systems courses like UC Berkeley's EECS 151, which provides actionable, synthesis-aware feedback without code edits. AutoTA improves student understanding of synthesis issues and optimizes the feedback loop between instructors and students.}
}

EndNote citation:

%0 Thesis
%A Kanagal, Rohit
%T LLM-Powered EDA Log Analysis for Effective Design Debugging
%I EECS Department, University of California, Berkeley
%D 2025
%8 May 12
%@ UCB/EECS-2025-48
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2025/EECS-2025-48.html
%F Kanagal:EECS-2025-48