PhD Candidate
Yale University
Areas of Interest
- Computer Architecture and Engineering
- Security
- Hardware Verification
Poster
Securing Modern Processors: Secure Processor TLBs, Caches, and Beyond
Abstract
My research includes developing and verifying secure processor microarchitectures by self-developing timing side-channel vulnerability checking schemes, as well as proposing languages and tools for practical and scalable security hardware and architectures verification. My work provides a new modeling approach to enumerate and understand all possible timing-based vulnerabilities in caches and Translation Lookaside Buffers (TLBs) and provide corresponding hardware defenses. A novel three-step modeling approach is proposed to exhaustively enumerate all possible timing-based vulnerabilities for caches and TLBs. I also propose two new secure TLB designs to defend not only against the previously publicized attacks but also against other new timing-based attacks in TLBs found using my new three-step model. Regarding hardware security verification, I develop design-time security verification frameworks for secure processor architectures. As the computing field moves forward quickly, I want to ensure that future computers are secure by extending my work on timing channels in classical computers to Arm processors and AI processors.
Bio
I am now a fifth-year PhD candidate at Computer Architecture and Security Lab (CASLAB) at Yale University, under the supervision of Professor Jakub Szefer. My current research includes developing and verifying secure processor microarchitectures by self-developing timing side-channel vulnerability checking schemes, as well as proposing languages and tools for practical and scalable security hardware and architectures verification.
