C. Hu, Ed., Nonvolatile Semiconductor Memories: Technologies, Design, and Applications, IEEE Press Selected Reprint Series, New York: Institute of Electrical and Electronics Engineers, 1991.
C. Hu and R. M. White, Solar Cells: From Basics to Advanced Systems, McGraw-Hill Series in Electrical Engineering: Power and Energy, New York: McGraw-Hill, 1983.
Book chapters or sections
M. Dunga, C. Lin, A. Niknejad, and C. Hu, "BSIM-CMG: A Compact Model for Multi-Gate Transistors," in FinFETs and Other Multi-Gate Transistors, Springer, 2008, pp. 113-153.
M. V. Dunga, C. Lin, A. Niknejad, and C. Hu, "BSIM-CMG: A compact model for multi-gate transistors," in FinFETs and Other Multi-Gate Transistors, J. P. Colinge, Ed., Integrated Circuits and Systems, New York, NY: Springer Science+Business Media, LLC, 2007, pp. 113-153.
Articles in journals or magazines
C. K. Dabhi, D. Nandi, K. Nandan, D. Rajasekharan, G. Pahwa, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Symmetric BSIM-SOI—Part II: A Compact Model for Partially Depleted SOI MOSFETs," IEEE Transactions on Electron Devices, pp. 1-8, 2024.
C. K. Dabhi, D. Rajasekharan, G. Pahwa, D. Nandi, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Symmetric BSIM-SOI—Part I: A Compact Model for Dynamically Depleted SOI MOSFETs," IEEE Transactions on Electron Devices, pp. 1-9, Feb. 2024.
S. B. Desai, S. R. Madhvapathy, A. B. Sachid, J. P. Llinas, Q. Wang, G. H. Ahn, G. Pitner, M. J. Kim, J. Bokor, C. Hu, H. P. Wong, and A. Javey, "MoS2 transistors with 1-nanometer gate lengths," Science, vol. 354, no. 6308, pp. 99--102, Oct. 2016.
S. B. Desai, S. R. Madhvapathy, A. B. Sachid, J. P. Llinas, Q. Wang, G. H. Ahn, G. Pitner, M. J. Kim, J. Bokor, C. Hu, H. P. Wong, and A. Javey, "MoS2 transistors with 1-nanometer gate lengths," Science, vol. 354, no. 6308, pp. 99--102, Oct. 2016.
T. Roy, M. Tosun, J. S. Kang, A. B. Sachid, S. B. Desai, M. Hettick, C. Hu, and A. Javey, "Field-effect transistors built from all two-dimensional material components," ACS nano, vol. 8, no. 6, pp. 6259--6264, 2014.
A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, T. King Liu, and C. Hu, "MOSFET design of forward body biasing scheme," IEEE Electron Device Letters, vol. 27, no. 5, pp. 387-389, May 2006.
S. Lam, H. Wan, P. Su, P. Wyatt, C. Chen, A. Niknejad, C. Hu, P. Ko, and M. Chan, "RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology," IEEE Electron Device Letters, vol. 24, pp. 251-253, April 2003.
P. Su, S. Fung, P. Wyatt, W. Hui, A. Niknejad, M. Chan, and C. Hu, "On the body-source built-in potential lowering of SOI MOSFETs," IEEE Electron Device Letters, vol. 24, pp. 90-92, Feb. 2003.
D. Hisamoto, W. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. King Liu, J. Bokor, and C. Hu, "FinFET--A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
K. F. Schuegraf and C. Hu, "Reliability of thin SiO2," Semiconductor Science and Technology, vol. 9, no. 5, pp. 989-1004, May 1994.
Y. Fong, G. C. Liang, T. Van Duzer, and C. Hu, "Channel width effect on MOSFET breakdown," IEEE Trans. Electron Devices, vol. 39, no. 5, pp. 1265-1267, May 1992.
C. Hu, "IC reliability simulation," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 241-246, March 1992.
M. S. Chang, P. Burlamacchi, C. Hu, and J. R. Whinnery, "Light amplification in a thin film," Applied Physics Letters, vol. 20, no. 8, pp. 313-314, April 1972.
Articles in conference proceedings
S. Venugopalan, Y. Chauhan, D. Lu, M. Karim, A. Niknejad, and C. Hu, "Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations," in Non-Volatile Memory Technology Symposium (NVMTS), 2011 11th Annual, 2011, pp. 1 -4.
V. Sriramkumar, D. Lu, T. Morshed, Y. Kawakami, P. Lee, A. Niknejad, and C. Hu, "BSIM-CG: A compact model of cylindrical gate / nanowire MOSFETs for circuit simulations," in VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, 2011, pp. 1 -2.
C. Lin, M. V. Dunga, D. D. Lu, A. Niknejad, and C. Hu, "Statistical compact modeling of variations in nano MOSFETs," in Proc. 2008 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '08), Piscataway, NJ: IEEE Press, 2008, pp. 165-166.
C. Hu, C. H. Lin, M. Dunga, D. Lu, and A. Niknejad, "A versatile multi-gate MOSFET compact model: BSIM-MG (Invited Paper)," in 6th Workshop on Compact Modeling (WCM 2007), Vol. 3, Cambridge, MA: Nano Science and Technology Institute, 2007.
C. Lin, M. V. Dunga, A. Niknejad, and C. Hu, "A compact quantum-mechanical model for double-gate MOSFET," in Proc. 8th Intl. Conf. on Solid-State and Integrated Circuit Technology (ICSICT-2006), T. Tang, G. Ru, and Y. Jiang, Eds., Piscataway, NJ: IEEE Press, 2006, pp. 1272-1274.
A. Niknejad, M. V. Dunga, B. Heydari, H. Wan, C. Lin, S. Emami Neyestanak, C. Doan, X. Xi, J. He, and C. Hu, "Challenges in compact modeling for RF and microwave applications," in Workshop on Compact Modeling, 2005, pp. N/A.
J. He, J. Xi, M. Chan, H. Wan, M. V. Dunga, B. Heydari, A. Niknejad, and C. Hu, "Charge-based core and the model architecture of BSIM5," in Quality of Electronic Design, 2005, pp. 96-101.
A. Niknejad, C. Doan, S. Emami Neyestanak, M. V. Dunga, X. Xi, J. He, R. W. Brodersen, and C. Hu, "Next generation CMOS compact mofels for RF and microwave applications (Invited)," in RFIC Digest of Papers, 2005, pp. 141-144.
X. Xi, J. He, M. V. Dunga, C. Lin, B. Heydari, H. Wan, M. Chan, A. Niknejad, and C. Hu, "The next generation BSIM for sun-100nm mixed-signal circuit simulation," in Proceedings of CICC, 2004, pp. 13-16.
M. Chan, C. Lin, J. He, Y. Taur, A. Niknejad, and C. Hu, "A framework for modeling double-Gate MOSFETs," in Workshop on Compact Modeling, 2003, pp. N/A.
J. He, X. Xi, M. Chan, A. Niknejad, and C. Hu, "An advanced surface-potential-plus MOSFET model," in Workshop on Compact Modeling, 2003, pp. N/A.
M. V. Dunga, X. Xi, J. He, I. Polishchuk, Q. Lu, M. Chan, A. Niknejad, and C. Hu, "Modeling of direct tunneling current in multi-layer gate stacks," in Workshop on Compact Modeling, 2003, pp. N/A.
A. Niknejad, M. Chan, C. Hu, X. Xi, J. He, P. Su, Y. Cao, H. Wan, M. V. Dunga, C. Doan, S. Emami Neyestanak, and C. Lin, "Compact modeling for RF and microwave applications (Invited)," in Workshop on Compact Modeling, 2003, pp. N/A.
C. Lin, J. He, X. Xi, H. Kam, A. Niknejad, M. Chan, and C. Hu, "The impact of scaling on volume inversion in symmetric double-gate MOSFETs," in Semiconductor Device Research Symposium, 2003, pp. 148-149.
C. Lin, P. Su, Y. Taur, X. Xi, J. He, A. Niknejad, M. Chan, and C. Hu, "Circuit performance of double-gate SOI CMOS," in Semiconductor Device Research Symposium, 2003, pp. 266-267.
P. Su, S. Fung, P. Wyatt, H. Wan, M. Chan, A. Niknejad, and C. Hu, "A unified model for partial-depletion and full depletion SOI circuit designs: Using BSIMPD as a foundation," in Proceedings of CICC, 2003, pp. N/A.
P. Su, S. Fung, H. Wan, A. Niknejad, M. Chan, and C. Hu, "An impact ionization model for SOI circuit simulation," in IEEE International SOI Conference, 2002, pp. 201-202.
B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
M. Orshansky, C. Hu, and C. J. Spanos, "Circuit performance variability decomposition," in Proc. 4th Intl. Workshop on Statistical Metrology (IWSM 1999), Piscataway, NJ: IEEE Press, 1999, pp. 10-13.
Technical Reports
W. Liu, X. Jin, K. Cao, and C. Hu, "BSIM 4.1.0 MOSFET Model-User's Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/48, Oct. 2000.
W. Liu, K. Cao, X. Jin, and C. Hu, "BSIM 4.0.0 Technical Notes," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/39, Aug. 2000.
W. Liu, X. Jin, K. Cao, and C. Hu, "BSIM 4.0.0 MOSFET Model User's Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/38, Aug. 2000.
W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, "BSIM3v3.2.1 MOSFET Model Users' Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/19, March 1999.
W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, "BSIM3v3.2.2 MOSFET Model Users' Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/18, March 1999.
W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, "BSIM 3v3.2 MOSFET Model Users' Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/51, Aug. 1998.
Y. Cheng, M. Chan, K. Hui, M. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu, P. Ko, and C. Hu, "BSIM 3v3 Manual (Final Version)," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/2, Jan. 1997.
J. Huang, Z. Liu, M. Jeng, P. Ko, and C. Hu, "A Physical Model for MOSFET Output Resistance," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/56, July 1993.
R. Tu, E. Rosenbaum, C. Li, W. Chan, P. Lee, B. Liew, J. Burnett, P. Ko, and C. Hu, "BERT - Berkeley Reliability Tools," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/107, Dec. 1991.
B. Liew, P. Fang, N. W. Cheung, and C. Hu, "BERT - Circuit Electromigration Simulator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/3, Jan. 1990.
P. Lee, M. Kuo, P. Ko, and C. Hu, "BERT - Circuit Aging Simulator (CAS)," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/2, Jan. 1990.
C. Lin, W. Lee, Y. Yeo, C. Lin, and C. Hu, "A method for forming a device having multiple silicide types," U.S. Patent Application. Aug. 2006.
C. Ko, W. Lee, Y. Yeo, C. Lin, and C. Hu, "Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit," U.S. Patent Application. July 2006.
C. Ko, Y. Yeo, W. Lee, and C. Hu, "Strained channel complementary field-effect transistors and methods of manufacture," U.S. Patent Application. April 2006.
W. Lee, C. Ke, and C. Hu, "Semiconductor structure having a strained region and a method of fabricating same," U.S. Patent Application. April 2006.
C. Huang, C. Wang, C. Ge, and C. Hu, "CMOS device," U.S. Patent 7,022,561. April 2006.
C. Huang, C. Wang, C. Ge, and C. Hu, "Novel CMOS device," U.S. Patent Application. Feb. 2006.
Y. Yeo and C. Hu, "Capacitor that includes high permittivity capacitor dielectric," U.S. Patent Application. Jan. 2006.
Y. Yeo and C. Hu, "SOI chip with recess-resistant buried insulator and method of manufacturing the same," U.S. Patent Application. Dec. 2005.
Y. Yeo, C. Lin, F. Yang, and C. Hu, "Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer," U.S. Patent Application. Sep. 2005.
Y. Yeo, C. Lin, W. Lee, and C. Hu, "Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof," U.S. Patent Application. Aug. 2005.
C. Ke, W. Lee, and C. Hu, "Semiconductor structure having selective silicide-induced stress and a method of producing same," U.S. Patent Application. Aug. 2005.
C. Huang, F. Yang, M. Ken, C. Hu, C. Ge, W. Lee, and C. Ko, "Complementary field-effect transistors and methods of manufacture," U.S. Patent Application. July 2004.
H. Chen, Y. Chan, K. Yang, F. Yang, and C. Hu, "Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement," U.S. Patent Application. July 2004.
C. Wang, S. Chen, Y. Wang, H. Chiu, L. Yao, and C. Hu, "Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same," U.S. Patent Application. June 2004.
W. Lee, C. Ge, and C. Hu, "Silicide/semiconductor structure and method of fabrication," U.S. Patent Application. June 2004.
C. Huang, Y. Yeo, C. Wang, C. Lin, and C. Hu, "Improved cobalt silicidation process for substrates with a silicon germanium layer," U.S. Patent Application. June 2004.
Y. Yeo and C. Hu, "Lithography apparatus for manufacture of integrated circuits," U.S. Patent Application. April 2004.
Y. Yeo, B. Lin, and C. Hu, "Immersion fluid for immersion lithography, and method of performing immersion lithography," U.S. Patent Application. March 2004.
C. Wang and C. Hu, "Devices with high-k gate dielectric," U.S. Patent Application. Jan. 2004.
C. Lin, W. Lee, Y. Yeo, and C. Hu, "Structure and method of forming integrated circuits utilizing strained channel transistors," U.S. Patent Application. Dec. 2003.
Y. Yeo, C. Wang, and C. Hu, "Dummy pattern for silicide gate electrode," U.S. Patent Application. Oct. 2003.
C. Lin, W. Lee, Y. Yeo, and C. Hu, "Ultra-thin body transistor with recessed silicide contacts," U.S. Patent Application. Aug. 2003.
Y. Yeo, F. Yang, and C. Hu, "Semiconductor diode with reduced leakage," U.S. Patent Application. Aug. 2003.
C. Hu, D. Tang, and H. Tseng, "Semiconductor device with low-k dielectric in close proximity thereto and its method of fabrication," U.S. Patent Application. Aug. 2003.
Y. Yeo and C. Hu, "Capacitor with improved capacitance density and method of manufacture," U.S. Patent Application. July 2003.
Y. Yeo, F. Yang, and C. Hu, "Accumulation mode multiple gate transistor," U.S. Patent Application. May 2003.
H. Tseng, D. Lin, K. Yang, and C. Hu, "Method of fabricating a salicided device using a dummy dielectric layer between the source/drain and the gate electrode," U.S. Patent Application. March 2003.
N. W. Cheung, X. Lu, and C. Hu, "Method of separating films from bulk substrates by plasma immersion ion implantation," U.S. Patent Application. May 2001.