# Faculty Publications - Borivoje Nikolic

## Books

- J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic,
*Digital Integrated Circuits: A Design Perspective*, 2nd ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Pearson Education, 2003. - J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic,
*Digital Integrated Circuits: A Design Perspective*, 2 ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Prentice Hall/Pearson Education, 2003.

## Book chapters or sections

- L. T. Wang, W. J. Poppe, L. Pang, A. R. Neureuther, E. Alon, and B. Nikolic, "Hypersensitive parameter-identifying ring oscillators for lithography process monitoring," in
*Design for Manufacturability Through Design-Process Integration II*, V. K. Singh and M. L. Rieger, Eds., Proceedings of SPIE, Vol. 6925, Bellingham, WA: SPIE -- Society of Photo-Optical Instrumentation Engineers, 2008, pp. 69250P-1-10. - H. Liu, V. Dai, A. Zakhor, and B. Nikolic, "Reduced complexity compression algorithms for direct-write maskless lithography systems," in
*Emerging Lithographic Technologies X*, M. J. Lercel, Ed., Proceedings of SPIE, Vol. 6151, Bellingham, WA: SPIE -- Society for Photo-Optical Instrumentation Engineers, 2006, pp. 2B-1-14.

## Articles in journals or magazines

- V. Narasimha Swamy, P. {Rigge}, G. Ranade, B. Nikolic, and A. Sahai, "Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications,"
*IEEE Journal on Selected Areas in Communications*, vol. 37, no. 4, pp. 705-720, Feb. 2019. - V. Narasimha Swamy, S. {Suri}, P. {Rigge}, M. {Weiner}, G. Ranade, A. Sahai, and B. Nikolic, "Real-Time Cooperative Communication for Automation Over Wireless,"
*IEEE Transactions on Wireless Communications*, vol. 16, no. 11, pp. 7168-7183, Aug. 2017. - Y. Lee, A. Waterman, H. Cook, B. Zimmer, B. Keller, A. Puggelli, J. Kwak, R. Jevtic, S. Bailey, M. Blagojevic, B. Nikolic, D. A. Patterson, and K. Asanovic, "An agile approach to building RISC-V microprocessors,"
*IEEE Micro*, vol. 36, no. 2, pp. 8--20, 2016. - J. Kwak and B. Nikolic, "A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI,"
*IEEE Journal of Solid-State Circuits*, vol. 51, no. 10, pp. 2368-2379, Oct. 2016. - B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtić, B. Keller, S. Bailey, M. Blagojević, P. F. Chiu, H. P. Le, P. H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanović, and B. Nikolic, "A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC #x2013;DC Converters in 28 nm FDSOI,"
*IEEE Journal of Solid-State Circuits*, vol. 51, no. 4, pp. 930-942, April 2016. - A. Puglielli, A. Townley, G. LaCaille, V. Milovanović, P. Lu, K. Trotskovsky, A. Whitcombe, N. Narevsky, G. Wright, T. Courtade, E. Alon, B. Nikolic, and A. Niknejad, "Design of Energy- and Cost-Efficient Massive MIMO Arrays,"
*Proceedings of the IEEE*, vol. 104, no. 3, pp. 586-606, March 2016. - D. Stepanovic and B. Nikolic, "A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,"
*Solid-State Circuits, IEEE Journal of*, vol. 48, no. 4, pp. 971-982, April 2013. - S. D. Vamvakos, V. Stojanovic, and B. Nikolic, "Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis,"
*IEEE Transactions on Circuits and Systems I: Regular Papers*, vol. 58, no. 6, pp. 1211-1224, 2011. - S. O. Toh, Z. Guo, T. King Liu, and B. Nikolic, "Characterization of Dynamic SRAM Stability in 45 nm CMOS,"
*Solid-State Circuits, IEEE Journal of*, vol. 46, no. 11, pp. 2702-2712, Nov. 2011. - Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, "An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors,"
*Solid-State Circuits, IEEE Journal of*, vol. 45, no. 4, pp. 843-855, April 2010. - Z. Guo, A. Carlson, L. Pang, K. Duong, T. King Liu, and B. Nikolic, "Large-Scale SRAM Variability Characterization in 45 nm CMOS,"
*Solid-State Circuits, IEEE Journal of*, vol. 44, no. 11, pp. 3174-3192, Nov. 2009. - B. Nikolic, "Design in the power-limited scaling regime (Invited Paper),"
*IEEE Trans. Electron Devices*, vol. 55, no. 1, pp. 71-83, Jan. 2008. - D. Markovic, B. Nikolic, and R. W. Brodersen, "Power and area minimization for multidimensional signal processing,"
*IEEE J. Solid-State Circuits*, vol. 42, no. 4, pp. 922-934, April 2007. - H. Liu, V. Dai, A. Zakhor, and B. Nikolic, "Reduced complexity compression algorithms for direct-write maskless lithography systems,"
*SPIE J. Micro/Nanolithography, MEMS, and MOEMS*, vol. 6, no. 1, pp. 13007-1-12, Jan. 2007. - J. M. Rabaey, F. De Bernardinis, A. Niknejad, B. Nikolic, and A. L. Sangiovanni-Vincentelli, "Embedding mixed-signal design in systems-on-chip (Invited Paper),"
*Proc. IEEE*, vol. 94, no. 6, pp. 1070-1088, June 2006. - R. Zlatanovici and B. Nikolic, "Power-performance optimiztion for custom digital circuits,"
*J. Low Power Electronics*, vol. 2, no. 1, pp. 113-120, April 2006. - Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,"
*IEEE J. Solid-State Circuits*, vol. 39, no. 12, pp. 2139-2151, Dec. 2004. - D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods for true energy-performance optimization,"
*IEEE J. Solid-State Circuits*, vol. 39, no. 8, pp. 1282-1293, Aug. 2004. - Y. Shimazaki, R. Zlatanovici, and B. Nikolic, "A shared-well dual-supply-voltage 64-bit ALU,"
*IEEE J. Solid-State Circuits*, vol. 39, no. 3, pp. 494-500, March 2004. - E. Yeo, B. Nikolic, and V. Anantharam, "Iterative decoder architectures,"
*IEEE Communications Magazine*, vol. 41, no. 8, pp. 132-140, Aug. 2003. - E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels,"
*IEEE Trans. Magnetics*, vol. 37, no. 2, pt. 1, pp. 748-755, March 2001.

## Articles in conference proceedings

- D. Nikiforov, S. K. Dong, C. L. Zhang, S. Kim, B. Nikolic, Y. S. Shao, and K. S. Dong, "RoSE: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation," in
*Proceedings of the 50th Annual International Symposium on Computer Architecture*, 2023, pp. 1--15. - V. Narasimha Swamy, P. Rigge, G. Ranade, B. Nikolic, and A. Sahai, "Predicting wireless channels for ultra-reliable low-latency communications," in
*2018 IEEE International Symposium on Information Theory (ISIT)*, 2018, pp. 2609--2613. - S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra, Q. Huang, K. Kovacs, B. Nikolic, R. H. Katz, J. Bachrach, and K. Asanović, "FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud," in
*Proceedings of the 45th Annual International Symposium on Computer Architecture*, ISCA '18, Piscataway, NJ, USA: IEEE Press, 2018, pp. 29--42. - X. Xiao, A. Pratt, A. Niknejad, E. Alon, and B. Nikolic, "A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-use," in
*ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference*, 2016, pp. 181-184. - B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, and B. Nikolic, "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC," in
*ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference*, 2016, pp. 269-272. - A. Whitcombe, S. Taylor, M. Denham, V. Milovanović, and B. Nikolic, "On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS," in
*2016 46th European Solid-State Device Research Conference (ESSDERC)*, 2016, pp. 248-251. - S. Ramakrishnan, L. Calderin, A. Puglielli, E. Alon, A. Niknejad, and B. Nikolic, "A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage," in
*2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)*, 2016, pp. 1-2. - M. Blagojević, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, and B. Nikolic, "A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI," in
*2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)*, 2016, pp. 1-2. - V. Narasimha Swamy, P. Rigge, G. Ranade, A. Sahai, and B. Nikolic, "Network coding for high-reliability low-latency wireless control," in
*Wireless Communications and Networking Conference Workshops (WCNCW), 2016 IEEE*, 2016. - V. Narasimha Swamy, S. Suri, P. Rigge, M. Weiner, G. Ranade, A. Sahai, and B. Nikolic, "Cooperative communication for high-reliability low-latency wireless control," in
*Proceedings of the IEEE International Conference on Communications*, 2015, pp. 4380-4386. - N. Kuo, B. Yang, C. Wu, L. Kong, A. Wang, M. Reiha, E. Alon, A. Niknejad, and B. Nikolic, "A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers," in
*Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian*, 2014, pp. 345--348. - M. Weiner, M. Jorgovanvic, A. Sahai, and B. Nikolic, "Design of a low-latency, high-reliability wireless communication system for control applications," in
*Proceedings of the 2014 IEEE International Conference on Communications*, 2014, pp. 3829-3835. - H. Liu, B. Richards, A. Zakhor, and B. Nikolic, "Hardware Implementation of Block GC3 Lossless Compression Algorithm for Direct-Write Lithography Systems," in
*Proc. of SPIE Alternative Lithographic Technologies II*, Vol. 7637, SPIE, 2010. - A. Carlson, Z. Guo, L. T. Pang, T. King Liu, and B. Nikolic, "Compensation of systematic variations through optimal biasing of SRAM wordlines," in
*Proc. 2008 Custom Integrated Circuits Conf. (CICC '08)*, Piscataway, NJ: IEEE Press, 2008. - P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolic, and M. Wainwright, "Error floors in LDPC codes: Fast simulation, bounds and hardware emulation," in
*Proc. 2008 IEEE Intl. Symp. on Information Theory (ISIT 2008)*, Piscataway, NJ: IEEE Press, 2008, pp. 444-448. - Z. Guo, A. Carlson, L. Pang, K. Duong, T. King Liu, and B. Nikolic, "Large-scale read/write margin measurement in 45nm CMOS SRAM arrays," in
*Proc. 2008 IEEE Symp. on VLSI Circuits*, Piscataway, NJ: IEEE Press, 2008, pp. 42-43. - B. Nikolic, "Power-limited design (Invited Paper)," in
*Proc. 14th IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS 2007)*, Piscataway, NJ: IEEE Press, 2007, pp. 927-930. - B. Nikolic, "Towards efficient spectrum sharing (Invited Talk)," in
*Proc. 6th IEEE/Dallas Circuits and Systems Workshop on System-on-Chip (DCAS 2007)*, Piscataway, NJ: IEEE Press, 2007, pp. 6 pg. - Z. Zhang, R. Winoto, A. Bahai, and B. Nikolic, "Peak-to-average power ratio reduction in an FDM broadcast system," in
*Proc. 2007 IEEE Workshop on Signal Processing Systems (SiPS '07)*, Piscataway, NJ: IEEE Press, 2007, pp. 25-30. - R. Marculescu, B. Nikolic, and A. L. Sangiovanni-Vincentelli, ""Fresh air": The Emerging Landscape of Design for Networked Embedded Systems (Session Abstract)," in
*Proc. 5th IEEE/ACM Intl. Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007)*, New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 124-124. - D. Markovic, C. Chang, B. Richards, H. So, B. Nikolic, and R. W. Brodersen, "ASIC design and verification in an FPGA environment," in
*Proc. 29th IEEE Custom Integrated Circuits Conf. (CICC 2007)*, Piscataway, NJ: IEEE Press, 2007, pp. 737-740. - L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, and B. Nikolic, "Evaluation of the low frame error rate performance of LDPC codes using importance sampling," in
*Proc. 2007 IEEE Information Theory Workshop (ITW '07)*, Piscataway, NJ: IEEE Press, 2007, pp. 202-207. - Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, and B. Nikolic, "Quantization effects in low-density parity-check decoders," in
*Proc. 2007 IEEE Intl. Conf. on Communications (ICC '07)*, Piscataway, NJ: IEEE Press, 2007, pp. 6231-6237. - L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, "Analysis of absorbing sets for array-based LDPC codes," in
*Proc. IEEE International Conference on Communications (ICC '07)*, Piscataway, NJ: IEEE Press, 2007, pp. 6261-6268. - D. Fang, R. Roberts, and B. Nikolic, "A 6-b DAC and analog DRAM for a maskless lithography interface in 90nm CMOS," in
*Proc. 2006 IEEE Asian Solid-State Circuits Conf. (A-SSCC '06)*, Piscataway, NJ: IEEE Press, 2006, pp. 423-426. - Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. Wainwright, "Investigation of error floors of structured low-density parity-check codes by hardware emulation," in
*Proc. IEEE Global Telecommunications Conference (GLOBECOM '06)*, Piscataway, NJ: IEEE Press, 2006, pp. 1-6. - A. Parsons, D. Backer, C. Chang, D. Chapman, H. Chen, P. Crescini, C. de Jesus, C. Dick, P. Droz, D. MacMahon, K. Meder, J. Mock, V. Nagpal, B. Nikolic, A. Parsa, B. Richards, A. Siemion, J. Wawrzynek, D. Werthimer, and M. Wright, "PetaOp/Second FPGA signal processing for SETI and radio astronomy (Invited Paper)," in
*Conference Record for the 40th Asilomar Conf. on Signals, Systems and Computers (ACSSC 2006)*, M. B. Matthews, Ed., Piscataway, NJ: IEEE Press, 2006, pp. 2031-2035. - F. Sheikh, M. Ler, R. Zlatanovici, D. Markovic, and B. Nikolic, "Power-performance optimal DSP architectures and ASIC implementation (Invited Paper)," in
*Conference Record for the 40th Asilomar Conf. on Signals, Systems and Computers (ACSSC 2006)*, M. B. Matthews, Ed., Piscataway, NJ: IEEE Press, 2006, pp. 1480-1485. - A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. King Liu, and B. Nikolic, "FinFET SRAM with enhanced read/write margins," in
*Proc. 2006 IEEE Intl. SOI Conf. (SOI '06)*, Piscataway, NJ: IEEE Press, 2006, pp. 105-106. - B. Nikolic and L. Pang, "Measurements and analysis of process variability in 90nm CMOS (Invited Paper)," in
*Proc. 8th Intl. Conf. on Solid-State and Integrated Circuit Technology (ICSICT-2006)*, T. Tang, G. Ru, and Y. Jiang, Eds., Piscataway, NJ: IEEE Press, 2006, pp. 505-508. - D. Markovic, B. Nikolic, and R. W. Brodersen, "Power and area efficient VLSI architectures for communication signal processing," in
*Proc. 2006 IEEE Intl. Conf. on Communications (ICC '06)*, Vol. 7, Piscataway, NJ: IEEE Press, 2006, pp. 3223-3228. - D. Markovic, R. W. Brodersen, and B. Nikolic, "A 70GOPS, 34mW multi-carrier MIMO chip in 3.5mm2," in
*2006 Symp. on VLSI Circuits Digest of Technical Papers*, Piscataway, NJ: IEEE Press, 2006, pp. 158-159. - L. Pang and B. Nikolic, "Impact of layout on 90nm CMOS process parameter fluctuations," in
*2006 Symp. on VLSI Circuits Digest of Technical Papers*, Piscataway, NJ: IEEE Press, 2006, pp. 69-70. - S. D. Vamvakos, V. Stojanovic, J. L. Zerbe, C. W. Werner, D. Draper, and B. Nikolic, "PLL on-chip jitter measurement: Analysis and design," in
*2006 Symp. on VLSI Circuits Digest of Technical Papers*, Piscataway, NJ: IEEE Press, 2006, pp. 73-74. - C. W. Tsang, Y. Chiu, and B. Nikolic, "A 1.2V, 10.8mW, 500kHz sigma-delta modulator with 84dB SNDR and 96dB SFDR," in
*2006 Symp. on VLSI Circuits Digest of Technical Papers*, Piscataway, NJ: IEEE Press, 2006, pp. 162-163. - S. Kao, R. Zlatanovici, and B. Nikolic, "A 240ps 64b carry-lookahead adder in 90nm CMOS," in
*2006 IEEE Intl. Solid-State Circuits Conf. (ISSCC '06). Digest of Technical Papers*, L. C. Fujino, Ed., Vol. 49, Piscataway, NJ: IEEE Press, 2006, pp. 1735-1744. - Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in
*Proc. ISLPED '05*, Piscataway, NJ: IEEE, 2005, pp. 2-7. - B. Nikolic, B. Wild, V. Dai, Y. A. Shroff, B. Warlick, A. Zakhor, and W. G. Oldham, "Layout decompression chip for maskless lithography," in
*Proc. SPIE: Emerging Lithographic Technologies VIII*, R. S. Mackay, Ed., Vol. 5374, Bellingham, WA: SPIE, 2004, pp. 1092-1099. - E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "High throughput low-density parity-check decoder architectures," in
*Proc. 2001 IEEE Global Telecommunications Conf. (GLOBECOM '01)*, Vol. 5, Piscataway, NJ: IEEE Press, 2001, pp. 3019-3024.

## Technical Reports

- C. Celio, P. Chiu, B. Nikolic, D. A. Patterson, and K. Asanović, "BOOM v2: an open-source out-of-order RISC-V core," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-157, Sep. 2017.

## Patents

- M. M. T. Leung, L. K. C. Fu, B. Nikolic, and J. K. S. Chiu, "Simplified branch metric and method," U.S. Patent 6,704,903. March 2004.
- W. Jia and B. Nikolic, "Sense amplifier-based flip-flop with asynchronous set and reset," U.S. Patent 6,633,188. Oct. 2003.
- B. Nikolic, L. Fu, M. Leung, V. G. Oklobdzija, and R. Yamasaki, "Reduced-complexity sequence detection," U.S. Patent 6,553,541. April 2003.
- B. Nikolic and W. Jia, "Sense amplifier based flip-flop," U.S. Patent 6,107,853. Aug. 2000.
- B. Nikolic and M. Leung, "Sliding block (rate 8/9) trellis code for magnetic recording," U.S. Patent 6,081,210. June 2000.

## Ph.D. Theses

- A. Whitcombe, "Configurable Data Converters for Digitally Adaptive Radio," B. Nikolic, Ed., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-156, Dec. 2019.
- A. Puglielli, B. Nikolic, and E. Alon, "System Architecture and Signal Processing Techniques for Massive Multi-user Antenna Arrays," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-149, Dec. 2019.
- B. Keller, "Energy-Efficient System Design Through Adaptive Voltage Scaling," B. Nikolic, K. Asanović, and D. Callaway, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-146, Dec. 2019.
- Y. Qiao, "Variability-Aware Compact Modeling of Nano-scale Technologies with Customized Test Structure Designs," C. J. Spanos and B. Nikolic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2018-148, Dec. 2018.
- S. Ramakrishnan and B. Nikolic, "Design of Integrated Full-Duplex Wireless Transceivers," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-24, May 2017.
- C. Shin, "Advanced MOSFET Designs and Implications for SRAM Scaling," T. King Liu, B. Nikolic, and E. Haller, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2012-50, May 2012.
- J. Park and B. Nikolic, "Power-efficient Design of Multi-Gpbs Wireless Baseband," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2011-135, Dec. 2011.
- R. Winoto and B. Nikolic, "Downconverting Sigma-Delta A/D Converter for a Reconfigurable RF Receiver," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2009-81, May 2009.

## Masters Reports

- A. Nandakumar, "Accelerating Deep Learning on Heterogenous Architectures," S. Shao and B. Nikolic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2022-100, May 2022.
- J. Dunn, "An Open, Scalable Massive MIMO Testbed Operating at E-Band Frequencies," B. Nikolic, A. Niknejad, and E. Alon, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2020-194, Dec. 2020.
- Z. Liu, "Time-interleaved SAR ADC Design Using Berkeley Analog Generator," B. Nikolic and V. Stojanovic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2020-109, May 2020.
- A. Amid, "Nested-Parallelism PageRank on RISC-V Vector Multi-Processors," B. Nikolic and K. Asanović, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-6, April 2019.
- G. Choi, "A Multiplying Delay-Locked Loop For A Self-Adjustable Clock Generator," B. Nikolic, Ed., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-108, May 2017.
- Y. Toh, "BPSK Demodulation for RF Applications," A. Niknejad and B. Nikolic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-91, May 2017.
- A. Whitcombe, "Variability Characterization of Imaging Readout Integrated Circuits in Deeply Scaled CMOS," B. Nikolic, Ed., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-183, Dec. 2016.
- B. Keller, "Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency," B. Nikolic and K. Asanović, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-257, Dec. 2015.
- S. Twigg, "Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language," J. Wawrzynek and B. Nikolic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-256, Dec. 2015.
- S. Bailey, "Modeling Radiation-Induced Soft Errors in Logic and the Overhead of Resiliency Techniques," B. Nikolic, Ed., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-233, Dec. 2014.
- B. Zimmer, B. Nikolic, and K. Asanović, "Resilient Design Methodology for Energy-Efficient SRAM," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2013-37, May 2013.
- M. Weiner and B. Nikolic, "A High-Throughput, Flexible LDPC Decoder for Multi-Gb/s Wireless Personal Area Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2010-177, Dec. 2010.