J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Pearson Education, 2003.
J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2 ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Prentice Hall/Pearson Education, 2003.
Book chapters or sections
L. T. Wang, W. J. Poppe, L. Pang, A. R. Neureuther, E. Alon, and B. Nikolic, "Hypersensitive parameter-identifying ring oscillators for lithography process monitoring," in Design for Manufacturability Through Design-Process Integration II, V. K. Singh and M. L. Rieger, Eds., Proceedings of SPIE, Vol. 6925, Bellingham, WA: SPIE -- Society of Photo-Optical Instrumentation Engineers, 2008, pp. 69250P-1-10.
Y. Lee, A. Waterman, H. Cook, B. Zimmer, B. Keller, A. Puggelli, J. Kwak, R. Jevtic, S. Bailey, M. Blagojevic, B. Nikolic, D. A. Patterson, and K. Asanovic, "An agile approach to building RISC-V microprocessors," IEEE Micro, vol. 36, no. 2, pp. 8--20, 2016.
A. Puglielli, A. Townley, G. LaCaille, V. Milovanović, P. Lu, K. Trotskovsky, A. Whitcombe, N. Narevsky, G. Wright, T. Courtade, E. Alon, B. Nikolic, and A. Niknejad, "Design of Energy- and Cost-Efficient Massive MIMO Arrays," Proceedings of the IEEE, vol. 104, no. 3, pp. 586-606, March 2016.
S. D. Vamvakos, V. Stojanovic, and B. Nikolic, "Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 6, pp. 1211-1224, 2011.
D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods for true energy-performance optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.
D. Nikiforov, S. K. Dong, C. L. Zhang, S. Kim, B. Nikolic, Y. S. Shao, and K. S. Dong, "RoSE: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation," in Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023, pp. 1--15.
S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra, Q. Huang, K. Kovacs, B. Nikolic, R. H. Katz, J. Bachrach, and K. Asanović, "FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud," in Proceedings of the 45th Annual International Symposium on Computer Architecture, ISCA '18, Piscataway, NJ, USA: IEEE Press, 2018, pp. 29--42.
B. Keller, M. Cochet, B. Zimmer, Y. Lee, M. Blagojevic, J. Kwak, A. Puggelli, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, and B. Nikolic, "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC," in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 269-272.
N. Kuo, B. Yang, C. Wu, L. Kong, A. Wang, M. Reiha, E. Alon, A. Niknejad, and B. Nikolic, "A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers," in Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian, 2014, pp. 345--348.
H. Liu, B. Richards, A. Zakhor, and B. Nikolic, "Hardware Implementation of Block GC3 Lossless Compression Algorithm for Direct-Write Lithography Systems," in Proc. of SPIE Alternative Lithographic Technologies II, Vol. 7637, SPIE, 2010.
A. Carlson, Z. Guo, L. T. Pang, T. King Liu, and B. Nikolic, "Compensation of systematic variations through optimal biasing of SRAM wordlines," in Proc. 2008 Custom Integrated Circuits Conf. (CICC '08), Piscataway, NJ: IEEE Press, 2008.
B. Nikolic, "Power-limited design (Invited Paper)," in Proc. 14th IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS 2007), Piscataway, NJ: IEEE Press, 2007, pp. 927-930.
D. Markovic, C. Chang, B. Richards, H. So, B. Nikolic, and R. W. Brodersen, "ASIC design and verification in an FPGA environment," in Proc. 29th IEEE Custom Integrated Circuits Conf. (CICC 2007), Piscataway, NJ: IEEE Press, 2007, pp. 737-740.
Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, and B. Nikolic, "Quantization effects in low-density parity-check decoders," in Proc. 2007 IEEE Intl. Conf. on Communications (ICC '07), Piscataway, NJ: IEEE Press, 2007, pp. 6231-6237.
L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, "Analysis of absorbing sets for array-based LDPC codes," in Proc. IEEE International Conference on Communications (ICC '07), Piscataway, NJ: IEEE Press, 2007, pp. 6261-6268.
A. Parsons, D. Backer, C. Chang, D. Chapman, H. Chen, P. Crescini, C. de Jesus, C. Dick, P. Droz, D. MacMahon, K. Meder, J. Mock, V. Nagpal, B. Nikolic, A. Parsa, B. Richards, A. Siemion, J. Wawrzynek, D. Werthimer, and M. Wright, "PetaOp/Second FPGA signal processing for SETI and radio astronomy (Invited Paper)," in Conference Record for the 40th Asilomar Conf. on Signals, Systems and Computers (ACSSC 2006), M. B. Matthews, Ed., Piscataway, NJ: IEEE Press, 2006, pp. 2031-2035.
A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. King Liu, and B. Nikolic, "FinFET SRAM with enhanced read/write margins," in Proc. 2006 IEEE Intl. SOI Conf. (SOI '06), Piscataway, NJ: IEEE Press, 2006, pp. 105-106.
D. Markovic, R. W. Brodersen, and B. Nikolic, "A 70GOPS, 34mW multi-carrier MIMO chip in 3.5mm2," in 2006 Symp. on VLSI Circuits Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2006, pp. 158-159.
S. D. Vamvakos, V. Stojanovic, J. L. Zerbe, C. W. Werner, D. Draper, and B. Nikolic, "PLL on-chip jitter measurement: Analysis and design," in 2006 Symp. on VLSI Circuits Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2006, pp. 73-74.
S. Kao, R. Zlatanovici, and B. Nikolic, "A 240ps 64b carry-lookahead adder in 90nm CMOS," in 2006 IEEE Intl. Solid-State Circuits Conf. (ISSCC '06). Digest of Technical Papers, L. C. Fujino, Ed., Vol. 49, Piscataway, NJ: IEEE Press, 2006, pp. 1735-1744.
Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED '05, Piscataway, NJ: IEEE, 2005, pp. 2-7.
B. Nikolic, B. Wild, V. Dai, Y. A. Shroff, B. Warlick, A. Zakhor, and W. G. Oldham, "Layout decompression chip for maskless lithography," in Proc. SPIE: Emerging Lithographic Technologies VIII, R. S. Mackay, Ed., Vol. 5374, Bellingham, WA: SPIE, 2004, pp. 1092-1099.
C. Celio, P. Chiu, B. Nikolic, D. A. Patterson, and K. Asanović, "BOOM v2: an open-source out-of-order RISC-V core," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-157, Sep. 2017.
Y. Toh, "BPSK Demodulation for RF Applications," A. Niknejad and B. Nikolic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-91, May 2017.