Book chapters or sections

• E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon, "Stream computations organized for reconfigurable execution (SCORE)," in The Roadmap to Reconfigurable Computing: Proc. 10th Intl. Workshop on Field-Programmable Logic and Applications, R. W. Hartenstein and H. Grunbacher, Eds., Lecture Notes in Computer Science, Vol. 1896, London, UK: Springer-Verlag, 2000, pp. 605-614.
• K. Asanović, J. Beck, D. Johnson, B. Kingsbury, N. Morgan, and J. Wawrzynek, "Training Neural Networks with SPERT-II," in Parallel Architectures for Artificial Networks - Paradigms and Implementations, N. Sundararajan, Ed., Los Alamitos, CA: IEEE Computer Society Press, 1998, pp. 345-364.
• T. J. Callahan and J. Wawrzynek, "Instruction-level parallelism for reconfigurable computing," in Proc. 8th Intl. Workshop on Field-Programmable Logic and Applications: From FPGAs to Computing Paradigm, R. W. Hartenstein and A. Keevallik, Eds., Lecture Notes in Computer Science, Vol. 1482, London, UK: Springer-Verlag, 1998, pp. 248-257.
• J. Wawrzynek, "VLSI models for sound synthesis," in Current Directions in Computer Music Research, M. V. Mathews and J. R. Pierce, Eds., MIT Press Series in System Development Foundation Benchmark, Cambridge, MA: MIT Press, 1989, pp. 113-148.

Articles in journals or magazines

• K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, N. Morgan, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "A View of the Parallel Computing Landscape," Communications of the ACM, vol. 52, no. 10, pp. 56-67, Oct. 2009.
• J. M. Rabaey, D. Burke, K. Lutz, and J. Wawrzynek, "Workloads of the future," IEEE Design & Test of Computers, vol. 25, no. 4, pp. 358-365, July 2008.
• J. Wawrzynek, D. A. Patterson, M. Oskin, S. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanović, "RAMP: Research Accelerator for Multiple Processors," IEEE Micro, vol. 27, no. 2, pp. 46-57, March 2007.
• C. Chang, J. Wawrzynek, and R. W. Brodersen, "BEE2: A high-end reconfigurable computing system," IEEE Design and Test of Computers, vol. 22, no. 2, pp. 114-125, March 2005.
• T. J. Callahan, J. R. Hauser, and J. Wawrzynek, "The Garp architecture and C compiler," Computer, vol. 33, no. 4, pp. 62-69, April 2000.
• J. Wawrzynek, K. Asanovic, B. Kingsbury, D. Johnson, J. Beck, and N. Morgan, "Spert-II: A vector microprocessor system," Computer, vol. 29, no. 3, pp. 79-86, March 1996.
• K. Asanović, N. Morgan, and J. Wawrzynek, "Using Simulations of Reduced Precision Arithmetic to Design a Neuro-Microprocessor," Journal of VLSI Signal Processing, vol. 6, pp. 33-44, 1993.
• K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "Connectionist Network Supercomputer," International Journal of Neural Systems, vol. 4, no. 4, pp. 317-326, Dec. 1993.

Articles in conference proceedings

• Y. Yang, Q. Huang, B. Wu, T. Zhang, L. Ma, G. Gambardella, M. Blott, L. Lavagno, K. Vissers, and J. Wawrzynek, "Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded fpgas," in Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019, pp. 23--32.
• B. Zhang, N. Mor, J. Kolb, D. S. Chan, N. Goyal, K. Lutz, E. Allman, J. Wawrzynek, E. A. Lee, and J. D. Kubiatowicz, "The Cloud is Not Enough: Saving IoT from the Cloud," in Proceedings of the 7th USENIX Conference on Hot Topics in Cloud Computing, HotCloud'15, Berkeley, CA, USA: USENIX Association, 2015, pp. 21--21.
• N. Bani Asadi, C. W. Fletcher, E. N. Glass, K. Sachs, D. Burke, Z. Zhou, J. Wawrzynek, W. H. Wong, G. P. Nolan, and G. Gibeling, "ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs," in Proceedings of the 24th ACM International Conference on Supercomputing, ICS '10, New York, NY, USA: ACM, 2010, pp. 83--94.
• J. Wawrzynek, "Adventures with a Reconfigurable Research Platform (Keynote Address)," in Proc. 2007 Intl. Conf. on Field Programmable Logic and Applications (FPL '07), Piscataway, NJ: IEEE Press, 2007, pp. 3-3.
• A. Krasnov, A. Schultz, J. Wawrzynek, G. Gibeling, and P. Y. Droz, "Ramp Blue: A message-passing manycore system in FPGAs," in Proc. 2007 Intl. Conf. on Field Programmable Logic and Applications (FPL '07), K. Bertels, W. Najjar, A. van Genderen, and S. Vassiliadis, Eds., Piscataway, NJ: IEEE Press, 2007, pp. 54-61.
• A. Parsons, D. Backer, C. Chang, D. Chapman, H. Chen, P. Crescini, C. de Jesus, C. Dick, P. Droz, D. MacMahon, K. Meder, J. Mock, V. Nagpal, B. Nikolic, A. Parsa, B. Richards, A. Siemion, J. Wawrzynek, D. Werthimer, and M. Wright, "PetaOp/Second FPGA signal processing for SETI and radio astronomy (Invited Paper)," in Conference Record for the 40th Asilomar Conf. on Signals, Systems and Computers (ACSSC 2006), M. B. Matthews, Ed., Piscataway, NJ: IEEE Press, 2006, pp. 2031-2035.
• C. R. Baker, Y. Markovsky, J. van Greunen, J. M. Rabaey, J. Wawrzynek, and A. Wolisz, "ZUMA: A platform for smart-home environments," in Proc. 2nd IET Intl. Conf. on Intelligent Environments (IE 2006), Stevenage, UK: IET Press, 2006, pp. 51-60.
• J. van Greunen, Y. Markovsky, C. R. Baker, J. M. Rabaey, J. Wawrzynek, and A. Wolisz, "ZUMA: A platform for smart-home environments -- The case for infrastructure," in Proc. 2nd IET Intl. Conf. on Intelligent Environments (IE 2006), Vol. 1, Stevenage, UK: IET Press, 2006, pp. 257-266.
• Z. Hyder and J. Wawrzynek, "Best Paper Award: Defect tolerance in multiple-FPGA systems," in Proc. IEEE 15th Intl. Conf. on Field Programmable Logic and Applications (FPL2005), T. Rissa, S. Wilton, and P. Leong, Eds., Piscataway, NJ: IEEE Press, 2005, pp. 247-254.
• N. Weaver, J. Hauser, and J. Wawrzynek, "The SFRA: A corner-turn FPGA architecture," in Proc. 2004 ACM/SIGDA 12th Intl. Symp. on Field Programmable Gate Arrays, New York, NY: ACM Press, 2004, pp. 3-12.
• J. Yeh and J. Wawrzynek, "Compute-resource allocation for motion estimation in real-time video compression," in Conf. Record of the 37th Asilomar Conf. on Signals, Systems & Computers, M. B. Matthews, Ed., Vol. 2, Piscataway, NJ: IEEE Press, 2003, pp. 1558-1561.
• Y. Markovskiy, E. Caspi, R. Huang, J. Yeh, M. Chu, J. Wawrzynek, and A. DeHon, "Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine," in Proc. 2002 ACM/SIGDA 10th Intl. Symp. on Field-Programmable Gate Arrays, New York, NY: ACM Press, 2002, pp. 196-205.
• J. Lazzaro and J. Wawrzynek, "Compiling MPEG 4 structured audio into C," in 2001 Proc. of Workshop and Exhibition on MPEG-4, Piscataway, NJ: IEEE Press, 2001, pp. 5-8.
• T. J. Callahan and J. Wawrzynek, "Adapting software pipelining for reconfigurable computing," in Proc. 2000 Intl. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY: ACM Press, 2000, pp. 57-64.
• A. DeHon and J. Wawrzynek, "Reconfigurable computing: What, why, and implications for design automation," in Proc. 36th Annual ACM/IEEE Conf. on Design Automation, M. J. Irwin, Ed., New York, NY: ACM Press, 1999, pp. 610-615.
• W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon, "HSRA: High-speed, hierarchical synchronous reconfigurable array," in Proc. 1999 ACM/SIGDA 7th Intl. Symp. on Field Programmable Gate Arrays, New York, NY: ACM Press, 1999, pp. 125-134.
• M. Chu, N. Weaver, K. Sulimma, A. DeHon, and J. Wawrzynek, "Object oriented circuit-generators in Java," in Proc. 1998 IEEE Symp. on FPGAs for Custom Computing Machines, K. L. Pocek and J. M. Arnold, Eds., Los Alamitos, CA: IEEE Computer Society, 1998, pp. 158-166.
• T. J. Callahan, P. Chong, A. DeHon, and J. Wawrzynek, "Fast module mapping and placement for datapaths in FPGAs," in Proc. 1998 ACM/SIGDA 6th Intl. Symp. on Field Programmable Gate Arrays, New York, NY: ACM Press, 1998, pp. 123-132.
• J. R. Hauser and J. Wawrzynek, "Garp: A MIPS processor with a reconfigurable coprocessor," in Proc. 5th Annual IEEE Symp. on FPGAs for Custom Computing Machines, Los Alamitos, CA: IEEE Computer Society, 1997, pp. 12-21.
• J. Wawrzynek, K. Asanović, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan, "SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training," in Proceeding of NIPS 8, 1996, pp. 619-625.
• K. Asanović, J. Beck, B. Irissou, B. Kingsbury, N. Morgan, and J. Wawrzynek, "The T0 Vector Microprocessor," in Proceedings of Hot Chips VII, 1995.
• K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "A supercomputer for neural computation," in Proc. 1994 IEEE Intl. Conf. on Neural Networks (ICNN '94), Vol. 1, Piscataway, NJ: IEEE Press, 1994, pp. 5-9.
• K. Asanović, J. Beck, J. A. Feldman, N. Morgan, and J. Wawrzynek, "Development of a Connectionist Network Supercomputer," in Proceedings of Micro-Neuro 1993, 1993, pp. 253-262.
• J. Wawrzynek, K. Asanović, and N. Morgan, "The Design of a Neuro-Microprocessor," in Proceedings of IEEE Transactions on Neural Networks, Vol. 4, 1993, pp. 394-399.
• K. Asanović, J. Beck, B. Kingsubry, P. Kohn, N. Morgan, and J. Wawrzynek, "SPERT: A VLIW/SIMD Neuro-Microprocessor," in Proceedings of IJCNN '92, 1992, pp. II-577-582.
• D. E. Culler, A. Sah, K. E. Schauser, T. von Eicken, and J. Wawrzynek, "Fine-grain parallelism with minimal hardware support: A compiler-controlled threaded abstract machine," in Proc. 4th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, New York, NY: ACM Press, 1991, pp. 164-175.

Technical Reports

• A. Sahai, J. Wawrzynek, and F. Zhao, "Spectrum Access System: Comparison of Different Equalizers," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-87, May 2017.
• H. Sun, "Spectrum Access System: Design and Implementation of the Decision-Feedback Equalizer in Software," A. Sahai and J. Wawrzynek, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-65, May 2017.
• E. A. Lee, J. D. Kubiatowicz, J. M. Rabaey, A. L. Sangiovanni-Vincentelli, S. A. Seshia, J. Wawrzynek, D. Blaauw, P. Dutta, K. Fu, C. Guestrin, R. Jafari, D. Jones, V. Kumar, R. Murray, G. Pappas, A. Rowe, C. M. Sechen, T. S. Rosing, B. Taskar, and D. Wessel, "The TerraSwarm Research Center (TSRC) (A White Paper)," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2012-207, Nov. 2012.
• K. Asanović, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-23, March 2008.
• J. Wawrzynek, M. Oskin, C. Kozyrakis, D. Chiou, D. A. Patterson, S. Lu, J. C. Hoe, and K. Asanović, "RAMP: A Research Accelerator for Multiple Processors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-158, Nov. 2006.
• Arvind, K. Asanović, D. Chiou, J. C. Hoe, C. Kozyrakis, S. Lu, M. Oskin, D. Patterson, J. Rabaey, and J. Wawrzynek, "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-05-1412, Sep. 2005.
• K. Asanović, J. Beck, T. Callahan, J. A. Feldman, B. Irissou, B. Kingsbury, P. Kohn, J. Lazarro, N. Morgan, D. Stoutamire, and J. Wawrzynek, "CNS-1 Architecture Specification - A Connectionist Network Supercomputer," International Computer Science Institute, Tech. Rep. TR-93-021, 1993.
• K. Asanović, J. Beck, T. Callahan, J. Feldman, B. S. Irissou, B. Kingsbury, P. Kohn, J. Lazzaro, N. Morgan, D. Stoutamire, and J. Wawrzynek, "CNS-1 Architecture Specification," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-93-747, 1993.
• J. Wawrzynek and B. Irissou, "High Speed 64-b CMOS Datapath," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-93-750, June 1993.
• K. Asanović, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek, "Development of a Connectionist Network Supercomputer," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-93-749, June 1993.
• J. Lazzaro and J. Wawrzynek, "Low-Power Silicon Neurons, Axons, and Synapses," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-93-751, June 1993.
• B. Kingsbury, K. Asanović, B. Irissou, N. Morgan, and J. Wawrzynek, "Recent work in VLSI elements for digital implementations of Artificial Neural Networks," International Computer Science Institute, Tech. Rep. TR-91-074, 1991.
• K. Asanović, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek, "SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations," International Computer Science Institute, Tech. Rep. TR-91-072, 1991.
• D. E. Culler, A. Soh, K. E. Schauser, T. von Eicken, and J. Wawrzynek, "Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-90-594, April 1991.
• N. Morgan, K. Asanović, B. Kingsbury, and J. Wawrzynek, "Developments in Digital VLSI Design for Artificial Neural Networks," International Computer Science Institute, Tech. Rep. TR-090-065, 1990.
• J. Wawrzynek and T. von Eicken, "MIMIC, A Custom VLSI Parallel Processor for Musical Sound Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/CSD-90-578, July 1990.

Patents

• A. DeHon, R. Huang, and J. Wawrzynek, "Fast router and hardware-assisted fast routing method," U.S. Patent 7,342,414. March 2008.
• J. C. Wawrzynek and C. A. Mead, "Electronic system for synthesizing and combining voices of musical instruments," U.S. Patent 4,736,663. April 1988.
• C. A. Mead, J. C. Wawrzynek, and T. Lin, "Electronic musical instrument," U.S. Patent 4,736,333. April 1988.
• C. A. Mead and J. C. Wawrzynek, "CMOS logic circuit," U.S. Patent 4,716,312. Dec. 1987.

Talks or presentations

• D. A. Patterson and J. Wawrzynek, "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform," presented at IEEE International Symposium on Performance Analysis of Systems and Software, Austin, TX, March 2006.

Masters Reports

• M. Kang, A. Nova, E. Singh, G. S. Bathini, and Y. Viktorov, "Learned Formal Proof Strengthening for Efficient Hardware Verification," J. Wawrzynek, Ed., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2023-260, Dec. 2023.
• L. Brink, "Deep Networks for Equalization in Communications," A. Sahai and J. Wawrzynek, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2018-177, Dec. 2018.
• H. Sun, "Spectrum Access System: Design and Implementation of the Decision-Feedback Equalizer in Software," A. Sahai and J. Wawrzynek, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-112, May 2017.
• S. Twigg, "Flexible FFT Optimization and RTL Generation in the Chisel Hardware Design Language," J. Wawrzynek and B. Nikolic, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-256, Dec. 2015.
• N. Goyal, J. Wawrzynek, and J. D. Kubiatowicz, "Global Data Plane Router on Click," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-234, Dec. 2015.