S-H. Huang and Jan M. Rabaey

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M95/32

, 1995

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1995/ERL-95-32.pdf

Transformations for algorithm optimization have shown to be effective in high-level synthesis. When a large number of transformations are available, it is always difficult to determine which transformations should be applied and in what order. In this report, we propose a methodology which clearly addresses these issues and organizes them in a systematic fashion. The proposed methodology is composed of a set of sub-tasks including bottleneck identification (why transformations should be applied), algorithm partitioning (which parts of an algorithm should be transformed), transformation prediction/selection (which transformations to apply), transformation ordering (the order in which the transformations are applied), and transformation execution (how to apply the selected transformations). A framework based on this methodology and aimed at the optimization of speed, area or power consumption of custom DSP designs, is under development. Assisted by such a framework, designers can easily and quickly to apply a variety of transformations to explore the algorithmic design space to reach better designs.

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BibTeX citation:

@techreport{Huang:M95/32,
    Author= {Huang, S-H. and Rabaey, Jan M.},
    Title= {A Methodology to Apply Optimizing Transformations},
    Year= {1995},
    Month= {Feb},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1995/2765.html},
    Number= {UCB/ERL M95/32},
    Abstract= {Transformations for algorithm optimization have shown to be effective in high-level synthesis.  When a large number of transformations are available, it is always difficult to determine which transformations should be applied and in what order.  In this report, we propose a methodology which clearly addresses these issues and organizes them in a systematic fashion.  The proposed methodology is composed of a set of sub-tasks including bottleneck identification (why transformations should be applied), algorithm partitioning (which parts of an algorithm should be transformed), transformation prediction/selection (which transformations to apply), transformation ordering (the order in which the transformations are applied), and transformation execution (how to apply the selected transformations).  A framework based on this methodology and aimed at the optimization of speed, area or power consumption of custom DSP designs, is under development.  Assisted by such a framework, designers can easily and quickly to apply a variety of transformations to explore the algorithmic design space to reach better designs.},
}

EndNote citation:

%0 Report
%A Huang, S-H. 
%A Rabaey, Jan M. 
%T A Methodology to Apply Optimizing Transformations
%I EECS Department, University of California, Berkeley
%D 1995
%@ UCB/ERL M95/32
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1995/2765.html
%F Huang:M95/32