A. Horvath and S. Parsa and H. Y. Wong

EECS Department, University of California, Berkeley

Technical Report No. UCB/ERL M05/15

, 2005

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2005/ERL-05-15.pdf

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BibTeX citation:

@techreport{Horvath:M05/15,
    Author= {Horvath, A. and Parsa, S. and Wong, H. Y.},
    Title= {0.35um CMOS Process on Six-Inch Wafers - Baseline Report IV},
    Year= {2005},
    Month= {Apr},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2005/4316.html},
    Number= {UCB/ERL M05/15},
}

EndNote citation:

%0 Report
%A Horvath, A. 
%A Parsa, S. 
%A Wong, H. Y. 
%T 0.35um CMOS Process on Six-Inch Wafers - Baseline Report IV
%I EECS Department, University of California, Berkeley
%D 2005
%@ UCB/ERL M05/15
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2005/4316.html
%F Horvath:M05/15