Kyoungsub Shin

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2006-192

December 21, 2006

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-192.pdf

Suppression of short-channel effects (SCE) and reduction in device-to-device variability will be key challenges for transistor scaling in sub-45nm CMOS technologies. Multi-gate transistor structures such as the FinFET may eventually be needed to meet performance requirements in the sub-20nm gate length regime because SCE can be effectively suppressed without the need for high channel doping concentrations, resulting in enhanced carrier mobilities. However, these advanced device structures will likely require a metal gate technology that offers tunable work function to allow for threshold voltage (VT) adjustment for proper CMOS circuit operation.

Strained-Si has also been considered as a key technology for enhancing carrier mobilities via modification of the electronic band structure of the channel material. Optimization of the channel surface crystalline orientation can further increase on-state drive current (Ion), e.g., electron mobility is highest for a (100) Si channel surface while hole mobility is highest for a (110) Si channel surface. In this dissertation, various technologies for optimizing the performance of multi-gate Si MOSFETs are presented. Firstly, both symmetrical and asymmetrical double-gate MOSFET designs are considered and shown to be reasonably tolerant of process-induced variations. From device simulation results, it is found that both the SDG and ADG designs are reasonably tolerant of process-induced variations. Secondly, a molybdenum gate technology with tunable effective work function for threshold-voltage adjustment is presented. With high-temperature forming-gas annealing (HTFGA), the work functions of Mo gate electrodes are successfully tuned in the range 4.6eV to 5.1eV. It is also found that the tuned work function of Mo by HTFGA is not retained during the subsequent source/drain activation annealing step unless a TiN capping layer is used to prevent nitrogen out-diffusion. Finally, strain-induced mobility enhancement for multiple-gate (MuG) Si MOSFETs with optimized channel surface crystalline orientations for CMOS application ((100) NMOS and (110) PMOS, respectively) via a strained SOI substrate, strained SiNx capping layer, tensile metal gate, and/or biaxial tensile wafer bending is discussed. The impact of strain on device performance is shown to be well modeled using the classic bulk-Si piezoresistance (PR) coefficients.

Advisors: Tsu-Jae King Liu

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BibTeX citation:

@phdthesis{Shin:EECS-2006-192,
    Author= {Shin, Kyoungsub},
    Title= {Technologies for enhancing multi-gate Si MOSFET performance},
    School= {EECS Department, University of California, Berkeley},
    Year= {2006},
    Month= {Dec},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-192.html},
    Number= {UCB/EECS-2006-192},
    Abstract= {
Suppression of short-channel effects (SCE) and reduction in device-to-device variability will be key challenges for transistor scaling in sub-45nm CMOS technologies.  Multi-gate transistor structures such as the FinFET may eventually be needed to meet performance requirements in the sub-20nm gate length regime because SCE can be effectively suppressed without the need for high channel doping concentrations, resulting in enhanced carrier mobilities. However, these advanced device structures will likely require a metal gate technology that offers tunable work function to allow for threshold voltage (VT) adjustment for proper CMOS circuit operation. 

Strained-Si has also been considered as a key technology for enhancing carrier mobilities via modification of the electronic band structure of the channel material. Optimization of the channel surface crystalline orientation can further increase on-state drive current (Ion), e.g., electron mobility is highest for a (100) Si channel surface while hole mobility is highest for a (110) Si channel surface.
   
In this dissertation, various technologies for optimizing the performance of multi-gate Si MOSFETs are presented.  Firstly, both symmetrical and asymmetrical double-gate MOSFET designs are considered and shown to be reasonably tolerant of process-induced variations. From device simulation results, it is found that both the SDG and ADG designs are reasonably tolerant of process-induced variations.
 
Secondly, a molybdenum gate technology with tunable effective work function for threshold-voltage adjustment is presented. With high-temperature forming-gas annealing (HTFGA), the work functions of Mo gate electrodes are successfully tuned in the range 4.6eV to 5.1eV. It is also found that the tuned work function of Mo by HTFGA is not retained during the subsequent source/drain activation annealing step unless a TiN capping layer is used to prevent nitrogen out-diffusion.
 
Finally, strain-induced mobility enhancement for multiple-gate (MuG) Si MOSFETs with optimized channel surface crystalline orientations for CMOS application ((100) NMOS and (110) PMOS, respectively) via a strained SOI substrate, strained SiNx capping layer, tensile metal gate, and/or biaxial tensile wafer bending is discussed.  The impact of strain on device performance is shown to be well modeled using the classic bulk-Si piezoresistance (PR) coefficients.},
}

EndNote citation:

%0 Thesis
%A Shin, Kyoungsub 
%T Technologies for enhancing multi-gate Si MOSFET performance
%I EECS Department, University of California, Berkeley
%D 2006
%8 December 21
%@ UCB/EECS-2006-192
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-192.html
%F Shin:EECS-2006-192